Clock Tree Synthesis CTS

What is CTS?

• Process of balancing clock skew and Minimizing Insertion Delay in order to meet timing , power requirements and other requirements.
• Process of distributing clock signal to clock pins based on physical information.
•  Clock Buffer Tree is build to achieve the CTS goals.

CTS Goals:

• Meet CTS design rule constraints such as Maximum Transition Delay, Maximum Load Capacitance, Maximum Fanout,  Maximum Buffer Levels.
• Meet the clock tree targets such as Maximum skew, Min/Max Insertion Delay.

Checklist before Clock Tree Synthesis:

• The design is placed and optimized
• Power and Ground nets are pre-routed
• Acceptable Congestion
• Meet Timing Constraints (~0ns Slack)
• No DRC Violations Such as Max Tran, Max Cap
• High Fanout Nets (Reset , Enable Pins are synthesized with buffers)

How to check whether Design is ready for CTS or not?

check_physical_design -for_cts:

1. checks design placed or not

2. checks all clocks are defined or not

3.checks for clock roots are not hierarchical pins

check_clock_tree:

checks and warns if:

1. A clock source pin is hierarchical pin  

2. There are multiple clocks per Register

3. A clock tree has no synchronous pin

4. A generated clock with improperly specified Master clock.

MCMM: Multi-Corner Multi-Mod

What's MCMM

MCMM stands for: Multi-Corner Multi-Mode (static timing analysis )

What's a Mode

A mode is defined by a set of clocks, supply voltages, timing constraints, and libraries. It can also have annotation data, such as SDF or parasitics files.


Many chip have multiple modes such as functional modes, test mode, sleep mode, and etc.

What's a Corner

A corner is defined as a set of libraries characterized for process, voltage, and temperature variations.


Corners are not dependent on functional settings; they are meant to capture variations in the manufacturing process, along with expected variations in the voltage and temperature of the environment in which the chip will operate.

Example:

Multi-mode multi-corner (MMMC) analysis refers to performing STA across multiple operating modes, PVT corners and parasitic interconnect corners at the same time. For example, consider a DUA that has four operating modes (Normal, Sleep, Scan shift, Jtag), and is being analyzed at three PVT corners (WCS, BCF, WCL) and three parasitic interconnect corners (Typical, Min C, Min RC)

 

There are a total of thirty six possible scenarios at which all timing checks, such as setup, hold, slew, and clock gating checks can be performed. Running STA for all thirty six scenarios at the same time can be prohibitive in terms of runtime depending upon the size of the design. It is possible that a scenario may not be necessary as it may be included within another scenario, or a scenario may not be required. For example, the designer may determine
that scenarios 4, 6, 7 and 9 are not relevant and thus are not required. Also, it may not be necessary to run all modes in one corner, such as Scan shift or Jtag modes may not be needed in scenario 5. STA could be run on a single scenario or on multiple scenarios concurrently if multi-mode multicorner capability is available.

Congestion

Congestion needs to be analyzed after placement and the routing results depend on how congested your design is. Routing congestion may be localized. Some of the things that you can do to make sure routing is hassle free are:

Placement blockages: 

The utilization constraint is not a hard rule, and if you want to specifically avoid placement in certain areas, use placement blockages.
Soft blockages (buffer only)
Hard blockages (No std cells and buffers are allowed to Place)
Partial blockages (same as density screens)
Halo (same as soft blockage but blockage can also be moved w.r.t Macro.)

Macro-padding:

 Macro padding or placement halos around the macros are placement blockages around the edge of the macros. This makes sure that no standard cells are placed near the pin outs of the macros, thereby giving extra breathing space for the macro pin connections to standard cells.

Cell padding:

Cell Padding refers to placement clearance applied to std cells in PnR tools. This is typically done to ease placement congestion or reserve some space for future use down the flow.
For example typically people apply cell padding to the buffers/inverters used to build clock tree, so that space is reserved to insert DECAP cells near them after CTS.

Cell padding adds hard constraints to placement. The constraints are honored by cell legalization, CTS, and timing optimization, unless the padding is reset after placement so
those operations can use the reserved space. You can use cell padding to reserve space for routing.

The command "specifyCellPad" is used to specify the cell padding in SOC-Encounter.

This command adds padding on the right side of library cells during placement.

The padding is specified in terms of a factor that is applied to the metal2 pitch. For example, if you specify a factor of 2, the software ensures that there is additional clearance of two times the metal2 pitch on the right side of the specified cells.

Maximum Utilization constraint (density screens): 

Some tools let you specify maximum core utilization numbers for specific regions. If any region has routing congestion, utilization there can be reduced, thus freeing up more area for routing.
each tool is having this setting, check wityh your DA for the detail.

set_congestion_options -max_util .6 -coordinate {10 20 40 40}

Antenna effect

The antenna effect [plasma induced gate oxide damage] is an effect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits. The IC fabs normally supply antenna rules that must be obeyed to avoid this problem and violation of such rules is called an antenna violation. The real problem here is the collection of charge.

A net in an IC will have at least one driver (which must contain a source or drain diffusion or in newer technology implantation is used), and at least one receiver (which will consist of a gate electrode over a thin gate dielectric). Since the gate dielectric is very thin, the layer  will breakdown if the net somehow acquires a voltage somewhat higher than the normal operating voltage of the chip. Once the chip is fabricated, this cannot happen, since every net has at least some source/drain implant connected to it. The source/drain implant forms a diode, which breaks down at a lower voltage than the oxide (either forward diode conduction, or reverse breakdown), and does so non-destructively. This protects the gate oxide. But during the construction phase, if the voltage is build up to the breakdown level when not protected by this diode, the gate oxide will breakdown.

Antenna rules are normally expressed as an allowable ratio of metal area to gate area. There is one such ratio for each interconnect layer. Each oxide will have different rule.

Antenna violations must be fixed by the router. Connecting gate oxide to the highest metal layer, adding vias to near the gate oxide to connect to highest layers used and adding diode to the net near the gate are some fixes that can be applied. Adding diode rises the capacitance and makes circuit slower and consumes more power.

Aspect Ratio of Core/Block/Design

The Aspect Ratio of Core/Block/Design is given as:



 

The aspect ratios of different core shapes are given in below :

The Role of Aspect Ratio on the Design:

1. The aspect ratio effects the routing resources available in the design
2. The aspect ratio effects the congestion
3. The floorplanning need to be done depend on the aspect ratio
4. The placement of the standard cells also effect due to aspect ratio
5. The timing and there by the frequency of the chip also effects due to aspect ratio
6. The clock tree build on the chip also effect due to aspect ratio
7. The placement of the IO pads on the IO area also effects due to aspect ratio
8. The packaging also effects due to the aspect ratio
9. The placement of the chip on the board also effects
10. Ultimately every thing depends on the aspect ration of core/block/design

NON Default Rule: NDR Rules

NONDEFAULT rule. This is a routing rule that is, well, not the default! It usually consists of double-wide or triple-wide metal, and at least double-wide spacing, but it can be whatever you like as long as it follows DRC rules (no violating the min or max metal widths, for example). NONDEFAULT rules are typically used to route clock nets or other sensitive nets. If you are very lucky, your tech LEF came with some NONDEFAULT rules already defined. But this is not usually the case. Those of us who have been around a while always dreaded the creation of NONDEFAULT rules -- it's not difficult, but it is tedious to write out a large tech LEF section by hand.

Well, for some time now, EDI has had the ability to create NONDEFAULT rules for us! It's easy and fast. Here's how to do it:

Name your NONDEFAULT rule something descriptive, and then choose an existing rule to start from. In most cases, all you'll have so far is the Default rule. That's a great starting point. With the default rule width and spacing numbers right in front of you, it's easy to enter values that are twice or three times as large for a double- or triple-wide rule.

Now, the vias: the vias from the default rule (or whatever rule you chose as your starting point) will be listed. In most cases, it's fine to just use the default rule vias.

Finally, decide if you want the NONDEFAULT rule to follow Hard Spacing. This means that violations of the NONDEFAULT rule spacing are considered and flagged as true violations. Without Hard Spacing turned on, the NONDEFAULT spacing is followed as much as possible, but if it needs to be broken to complete the route or follow other routing/spacing rules, then it's not considered a violation.

When you click OK or Apply, the rule is created and exists in your design database. But here is the crucial part: we want to add this NONDEFAULT rule to our tech LEF. Let's say we named our NONDEFAULT rule "DblWide" and we'll output it to a temporary file called tmp.lef. At the EDI prompt, type:

Non-Default rules are mostly used for routing only as they determine the width of the wires. Particularly for clock routing when there is the issue of Clock tree structuring and then the clock tuning, you might want to increase or decrease the width of the wires due to the insertion delay/skew requirements. 

So in case you have wider wire, which means the sheet resistance is lower which means there is faster current.

Sometimes you might also want to make the clock tree as variable sliding widths like a "in a leaf"..And then the non default rule must be used.

Non default rule as far as We  know is very less used for signal routing. 

difference between crosstalk noise and crosstalk delay

\Noise: 
The term “noise” in electronic design generally means any undesirable deviation in voltage of a net that ought to have a constant voltage, such as a power supply or ground line. In CMOS circuits, this includes data signals being held constant at logic 1 or logic 0.

For noise analysis tool considers the cross-coupling between aggressor nets and victim nets.
it determines the worst-case noise bump or glitch on steady-state victim net.
Steady-state means that the net is constant at logic 1 or logic 0.
The main commands for noise analysis are the check_noise, update_noise, and report_noise commands, which operate in a manner similar to the check_timing, update_timing, and report_timing
Prime time gives the noise reports as
1.Above high 
2.Above Low
3.Below Low
4. Below high
There are many different causes of noise such as charge storage effects at p-n junctions, power supply noise, and substrate noise. However, the dominant noise effect in deep-submicron CMOS circuits is crosstalk noise

Crosstalk delay: Crosstalk delay is same as noise but in this case both the nets are not in a steady state. 
there is some transition happening on both the nets.
crosstalk delay depends on the propagating direction of the aggressor and victim nets which makes the transition slower or faster.

Note: for setup analysis tool add crosstalk delay to the timing path and for hold it subtract the delta delay from the cell delay.