how to set timing derate values on library cells for min analysis?

Question:

I would like to apply-specific max and min timing derates.  My worst-case library is Worst.db and my Best-case library is Best.db. Here are the commands that I used:

set_link_library "*Worst.db"

set_min_library worst -min_version Best

set_timing_derate -max -cell_delay -data -late 4.00 [get_lib_cells worst/BUF1]

set_timing_derate -min -cell_delay -data -early 1.5 [get_lib_cells Best/BUF1]

report_timing_derate

I found that the tool failed to apply the specified derate factors , as seen in reports generated from report_timing_derate and report_timing -derate .  How can I fix this?

Answer:

The set_min_library cmd creates an association between the max and min libraries.  when computing min library, the tool finds the corresponding cell from the associated min library. The tool expects you to specify main library to which the cells have been linked in the current design. In this case, max library must be specified in the set_timing_derate -min cmd, as follows:

set_min_derate -min -cell_delay -data -early 1.5 [get_lib_cells Worst/BUF1]

the cells link to the first library that they can be linked to. In the above setting, it is the Worst.db library. However, the min derating is applied to cells in the associated min library, thus getting the desired result.

Constraints for PVT Corners

Normally Best/Worst PVT means the Fastest/Slowest operating condition of the circuit: typical Best(fastest) PVT is {process: fast, voltage: low, temperature: low} while worst  (slowest) PVT is {process: slow, voltage: high, temperature: high }.

However, recent technology process encounters inverse temperature effect, where cells might function faster at certain high temperature than low temperature, Thus it is suggested that you consult with the cell library provider on what PVT is fastest & slowest.


Notes:
The process fast means, that all transistors on the chip have combination of parameters which gives the minimum cell delay.

Also, We should know about RC corners. The width and thickness of wires (metal) are also may vary from chip to chip ( even on one chip:).  So , for the setup check, we should use RCWorst corner for extraction and one of PVT corners that gives you the max cell delay.

Explanation of Deration and OCV

1) Derating is simply another way of adding margin to the design. This allows you to scale all delays by a certain percentage to increase margin. This is not an SDC constraint, but a variable to set within the tool run script.

2) OCV is a timing mode ( like a single or BC/WC). This allows you to use variation from the libraries in performing timing checks for ensuring worst case scenarios.

How to fix max transition time violations?

The max transition time is one of the three Design Rules ( max fanout, max transition, max capacitance).

It is much more important than setup/hold timing.
As we all know, in STA, the delay of each std. cells is calculated from looking up the NLDM ( non-linear delay model) tables which is defined in library. These tables are two factors: input transition time, and output load. The result of table is the delay value of cell under certain transition and output load.

If the input transition or output load is out of range is within but not the values in NDLM, interpolation is utilized to calculate.
If the input transition or output load is out of range of NLDM , ext-interpolation is used to calculation. But it is natural the result would be rather in-accurate.

So the STA will be rather in-accurate. Timing analysis is un-believable.
Now, you can understand how important max tran is.
-- one more reason of fixing max transition violation is that bigger transition will result in bigger DC
    power consumption.
-- The margin in 30% of max transition is allowed.
For example, if the constraint of max transition is 1 ns, then 1.3 ns is allowed.

PVT Corners

Generally in most user environments, the process, voltage, and the temperature (PVT) point is specified by referring to a predefined operating condition in  a specific timing library. The library operating condition provides the system with values for P, V, and T, and these then are used to calculate derating parameters and other aspects of the analysis.

However, these are situations when there are no predefined operating conditions in the user timing libraries or the pre-existing operating conditions are not consistent with the user's operating environment.

Defining Operating Conditions in PD using SoC Encounter

I am using SoC encounter for project. I want to introduce operating conditions into the flow.

1. How these operating conditions are defined?
2. Is it dependent on Synthesis & RTL?
3. On what basis these operating conditions are decided?
4. What is the difference between prePD and postPD netlist?

Answers:
1. Using setOptCond command.
2. No.
3. Normally best case and worst case operating conditions is used for SoC           encounter do timing optimization for setup and hold.
4. PostPD netlist has complete clock tree structure and so more accurate               timing analysis with wire capacitance.

On-Chip Variation Delay Analysis

During timing analysis, the tool uses the on-chip variation(OCV) mode to perform timing, which models the effects of variation in operating conditions across the chip. This mode performs a conservative timing analysis by simultaneously applying minimum and maximum delays to different paths.

For a setup check, the tool uses maximum delays for the launch clock path and data path and minimum delays for the capture clock path, as shown in the following figure.