Tie-High/Tie-Low Cells

Removing Tie Cells
Use the remove_tie_cells cmd if you want to remove any tie cells, which are preexisting in the design or inserted by the tool. The cmd replaces the original tie cell connections with proper direct tie-off connections and removes the tie cells.

The syntax is:
remove_tie_cells [-use_default_tie_net] list_of_tie_cells

To reconnect a leaf pin and a hierachical pin to tie-off, the tie net to be created or reused by 

remove_tie_cells is a direct tie net. A tie-off net named SNPS_LOGIC1 or SNPS_LOGIC0 is a direct tie net and is written out by the verilog writer as 1'b1 or 1'b0, respectively.

To connect to a hierarchical port, the tie net to be created by remove_tie_cells is an indirect tie net. A tie net named other than SNPS_LOGIC1 or SNPS_LOGIC0 is an indirect tie net. If the hierarchical port name is Q, the indirect tie-high net name created by this cmd is Q_SNPS_LOGIC1.

Tie-off connection during remove_tie_cells

Using Aliases

icc_shell> alias rt100 { report_timing -max_paths 100}
Above show that you can use the alias command to create a shortcut for the report_timing command.


icc_shell> unalias f* rt100
Use the unalias cmd removes alias definition created with the alias command.
For Example, to remove all alias beginning with f* and the rt100 alias.

setting timing constraints

At a minimum, the timing constraints must constain a clock definition for each clock signal, as well as input delay or output delay for each I/O port. This requirement ensures that all signal paths are constrained for timing.

You should also define the uncertainty, latency, and transition constraints for each clock by using the
set_clock_uncertainty, set_clock_latency, and set_clock_transition commands.

To read a SDC file, use the read_sdc cmd ( or choose File > Import > Read SDC).

icc_shell> read_sdc -version 1.7 design_name.sdc

Notes,
If the SDC file does not contain unit setting, they are derived from the main library.
If the SDC file does contain unit settings, they must be consistent with those in the main library.

IC Compiler does not optimize paths that are not constrained for timing. Before proceeding, use the check_timing cmd to verify that all paths are constrainted.
If the check_timing cmd reports unconstrained paths, run the report_timing_requirements cmd to verify that the unconstrained path are false paths ( the check_timing cmd considers false paths unconstrained).


To remove the timing constraints, use oe of the following cmds:
- remove_sdc
 this cmd removes the timing constraints set by SDC cmds.

- remove_ideal_network -all
 this cmd removes ideal_network attributes, latencies, and transition times.

- reset_design
 this cmd removes all attributes from the design, including timing constraints, optimization attributes,
 and physical information.

on-chip Variation ( -analysis_type on_chip_variation )

In the on-chip variation mode, IC Compiler perform a conservative analysis that allows both minimum and maximum delays to apply to different paths at the same time.
For a setup check, it uses maximum delays for the launch clock path and datapath and minimum delays for the capture clock path.
For a hold check, it uses minimum delays for the launch clock path and datapath and maximum delays for the capture clock path.

If you are performing simultaneous manimum and maximum timing analysis, the logic libraries specified by the link_library variable are used for both maximum and minimum timing information, unless you specify seperate minimum timing libraries by using the set_min_library cmd.
The set_min_library cmd associates a minimum timing library with a maximum timing library specified in the link_library variable.

For example,

icc_shell> set_app_var link_library " * maxlib.db"
icc_sehll> set_min_library maxlib.db -min_version minlib.db

to find out which libraries have been set to be the minimum and maximum libraries, use the list_libs cmd. In the generated report, a lowercase letter "m" appears next to the minimum library and an uppercase letter "M" appears next to the maximum library.

Physical DFT Flow in ICC

Design Compiler (DC) vs IC Compiler (ICC)

DC is a synthesis tool ( that convert RTL code into gate-level netlist and optimize it).

It may works with WLM and with TLUPlus files.  The using WLM mode is an old approach to synthesis. In this mode, DC does not know about floorplan, about real wires, so the output optimized netlist may not be suitable for PnR tool.  But when DC uses TLUPlus files ( for RC estimation) , it works with floorplan, it do some kind of real placement ( and even some kind of routing -- DC graphical license ), so the output netlist is optimal as input for PnR tool ( for ICC).

ICC is a PnR tool, and it works well in conjection with DC.

TLUPlus is a  binary table format that stores the RC coefficients. The TLUPlus models enable accurate RC extraction results by including the effects of width , space, density, and temperature on the resistance coefficients. For details about modeling these effects in the Interconnect Technology Format (ITF) file, see the StarRC documentation.

To use TLUPlus models for RC estimation and extraction, you specify the following files:

-- The map file, which matches the layer and via names in the Milkyway technology file with the           names in the ITF file.

-- The maximum TLUPlus model file.

-- The minimum TLUPlus model file (optional). Specifying the minimum TLUPlus file is necessary if the minimum and maximum operating conditions are different and the TLUPlus models have derating coefficients. In that case, the minimum file must be specified even if it is the same as the maximum file.

You specify these files by using the set_tlu_plus_files cmd ( or by choosing File > Set TLU+ in the GUI). You can specify TLUPlus file names with or without their full paths. If you do not include the paths, IC Compiler uses the search paths defined with the search_path variable.

For example,

icc_shell> set_tlu_plus_files \

     -tech2itf_map ./path/map_file_name.map \

     -max_tluplus ./path/worst_settings.tlup \

     -min_tluplus ./path/best_settings.tlup

After specifying the TLUPlus files, you should validate them by running the check_tlu_plus_files command.

How to calculate minimum spacing between two macros?

Distance between macros can be known from = ( number of pins of macros * pitch *2) / number of available routing layers

or

Generally space between macros are calculated distance = ( number of pins * pitch ) / (total number of available metals/2)

why we are dividing with 2 means ... vertical and horizontal metals so we are dividing.

For example:

We have 2 macros having the pins of 100 each macro and pitch=025 and available metals are 6.

then space between 2 macros = ( ( 100+100)*0.25/(6/2)   This distance you should provide between macros.

How we find the number of pins?

Select the macro and press "q". It will give property of that macro.  Check " No. of terminals" in that.