setting timing constraints

At a minimum, the timing constraints must constain a clock definition for each clock signal, as well as input delay or output delay for each I/O port. This requirement ensures that all signal paths are constrained for timing.

You should also define the uncertainty, latency, and transition constraints for each clock by using the
set_clock_uncertainty, set_clock_latency, and set_clock_transition commands.

To read a SDC file, use the read_sdc cmd ( or choose File > Import > Read SDC).

icc_shell> read_sdc -version 1.7 design_name.sdc

Notes,
If the SDC file does not contain unit setting, they are derived from the main library.
If the SDC file does contain unit settings, they must be consistent with those in the main library.

IC Compiler does not optimize paths that are not constrained for timing. Before proceeding, use the check_timing cmd to verify that all paths are constrainted.
If the check_timing cmd reports unconstrained paths, run the report_timing_requirements cmd to verify that the unconstrained path are false paths ( the check_timing cmd considers false paths unconstrained).


To remove the timing constraints, use oe of the following cmds:
- remove_sdc
 this cmd removes the timing constraints set by SDC cmds.

- remove_ideal_network -all
 this cmd removes ideal_network attributes, latencies, and transition times.

- reset_design
 this cmd removes all attributes from the design, including timing constraints, optimization attributes,
 and physical information.