Antenna effect

The antenna effect [plasma induced gate oxide damage] is an effect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits. The IC fabs normally supply antenna rules that must be obeyed to avoid this problem and violation of such rules is called an antenna violation. The real problem here is the collection of charge.

A net in an IC will have at least one driver (which must contain a source or drain diffusion or in newer technology implantation is used), and at least one receiver (which will consist of a gate electrode over a thin gate dielectric). Since the gate dielectric is very thin, the layer  will breakdown if the net somehow acquires a voltage somewhat higher than the normal operating voltage of the chip. Once the chip is fabricated, this cannot happen, since every net has at least some source/drain implant connected to it. The source/drain implant forms a diode, which breaks down at a lower voltage than the oxide (either forward diode conduction, or reverse breakdown), and does so non-destructively. This protects the gate oxide. But during the construction phase, if the voltage is build up to the breakdown level when not protected by this diode, the gate oxide will breakdown.

Antenna rules are normally expressed as an allowable ratio of metal area to gate area. There is one such ratio for each interconnect layer. Each oxide will have different rule.

Antenna violations must be fixed by the router. Connecting gate oxide to the highest metal layer, adding vias to near the gate oxide to connect to highest layers used and adding diode to the net near the gate are some fixes that can be applied. Adding diode rises the capacitance and makes circuit slower and consumes more power.

Aspect Ratio of Core/Block/Design

The Aspect Ratio of Core/Block/Design is given as:



 

The aspect ratios of different core shapes are given in below :

The Role of Aspect Ratio on the Design:

1. The aspect ratio effects the routing resources available in the design
2. The aspect ratio effects the congestion
3. The floorplanning need to be done depend on the aspect ratio
4. The placement of the standard cells also effect due to aspect ratio
5. The timing and there by the frequency of the chip also effects due to aspect ratio
6. The clock tree build on the chip also effect due to aspect ratio
7. The placement of the IO pads on the IO area also effects due to aspect ratio
8. The packaging also effects due to the aspect ratio
9. The placement of the chip on the board also effects
10. Ultimately every thing depends on the aspect ration of core/block/design

NON Default Rule: NDR Rules

NONDEFAULT rule. This is a routing rule that is, well, not the default! It usually consists of double-wide or triple-wide metal, and at least double-wide spacing, but it can be whatever you like as long as it follows DRC rules (no violating the min or max metal widths, for example). NONDEFAULT rules are typically used to route clock nets or other sensitive nets. If you are very lucky, your tech LEF came with some NONDEFAULT rules already defined. But this is not usually the case. Those of us who have been around a while always dreaded the creation of NONDEFAULT rules -- it's not difficult, but it is tedious to write out a large tech LEF section by hand.

Well, for some time now, EDI has had the ability to create NONDEFAULT rules for us! It's easy and fast. Here's how to do it:

Name your NONDEFAULT rule something descriptive, and then choose an existing rule to start from. In most cases, all you'll have so far is the Default rule. That's a great starting point. With the default rule width and spacing numbers right in front of you, it's easy to enter values that are twice or three times as large for a double- or triple-wide rule.

Now, the vias: the vias from the default rule (or whatever rule you chose as your starting point) will be listed. In most cases, it's fine to just use the default rule vias.

Finally, decide if you want the NONDEFAULT rule to follow Hard Spacing. This means that violations of the NONDEFAULT rule spacing are considered and flagged as true violations. Without Hard Spacing turned on, the NONDEFAULT spacing is followed as much as possible, but if it needs to be broken to complete the route or follow other routing/spacing rules, then it's not considered a violation.

When you click OK or Apply, the rule is created and exists in your design database. But here is the crucial part: we want to add this NONDEFAULT rule to our tech LEF. Let's say we named our NONDEFAULT rule "DblWide" and we'll output it to a temporary file called tmp.lef. At the EDI prompt, type:

Non-Default rules are mostly used for routing only as they determine the width of the wires. Particularly for clock routing when there is the issue of Clock tree structuring and then the clock tuning, you might want to increase or decrease the width of the wires due to the insertion delay/skew requirements. 

So in case you have wider wire, which means the sheet resistance is lower which means there is faster current.

Sometimes you might also want to make the clock tree as variable sliding widths like a "in a leaf"..And then the non default rule must be used.

Non default rule as far as We  know is very less used for signal routing. 

difference between crosstalk noise and crosstalk delay

\Noise: 
The term “noise” in electronic design generally means any undesirable deviation in voltage of a net that ought to have a constant voltage, such as a power supply or ground line. In CMOS circuits, this includes data signals being held constant at logic 1 or logic 0.

For noise analysis tool considers the cross-coupling between aggressor nets and victim nets.
it determines the worst-case noise bump or glitch on steady-state victim net.
Steady-state means that the net is constant at logic 1 or logic 0.
The main commands for noise analysis are the check_noise, update_noise, and report_noise commands, which operate in a manner similar to the check_timing, update_timing, and report_timing
Prime time gives the noise reports as
1.Above high 
2.Above Low
3.Below Low
4. Below high
There are many different causes of noise such as charge storage effects at p-n junctions, power supply noise, and substrate noise. However, the dominant noise effect in deep-submicron CMOS circuits is crosstalk noise

Crosstalk delay: Crosstalk delay is same as noise but in this case both the nets are not in a steady state. 
there is some transition happening on both the nets.
crosstalk delay depends on the propagating direction of the aggressor and victim nets which makes the transition slower or faster.

Note: for setup analysis tool add crosstalk delay to the timing path and for hold it subtract the delta delay from the cell delay.

FinFET Technology

A multigate device or multiple gate field-effect transistor (MuGFET) refers to a MOSFET (metal-oxide-semiconductor field effect transistor) which incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate , or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a Multiple Independent Gate Field Effect Transistor (MIGFET).

General MOSFET at submicron level is suffering from several submicron issues like short channel effects, threshold voltage variation etc. FinFET is supposed to overcome the short channel effects. Structure of of FinFET is shown in below,

Silicon on insulator (SOI) process is used to fabricate FinFET.  This process insures the ultra thin specifications of device regions. in FinFET electrical potential throughout the channel is controlled by the gate voltage. This is possible due to the proximity of gate control electrode to the current conduction path between source and drain. These characteristics of the FinFET minimize the short channel effect. Advantages of the FinFET over its bulk-si counterpart are as follows:
Conventional MOSFET manufacturing processes can also be used to fabricate FinFET.
FinFET provides better area efficiency compared to MOSFET.
mobiblity of the carriers can be improved by using FinFET process in conjunction with the strained silicon process.
FinFET device structure Silicon on Insulator (SOI) process is used to manufacture FinFET.  A single poly silicon layer is deposited over a fin. Thus poly silicon straddles the fin structure to form perfectly aligned gates. Here a fin itself acts as a channel and it terminates on both sides of source and drain.  In general MOSFET device, over the si substrate poly silicon gate is formed. Poly silicon gate controls the channel.  Straddling of poly silicon gate over the Si fin gives efficient gate controlled characteristics compared to MOSFET.  Since gate straddles the fin the length of the channel is same as that of width of the fin. As there are two gates effectively around the fin we can write, width of the channel is equivalent to twice the height of the fin i.e. w=2*h. A term called *fin pitch* is used to define the space between two fins. Height of the FinFET is equivalent to width of the MOSET.  If w is the fin pitch then to attain same area efficiency required fin height is w/2. But practical experiments have shown that fin height can be greater than w/2 for a fin pitch of w. thus FinFET achieves more area efficiency than MOSFET.

The basic electrical layout and the mode of operation of a FinFET does not differ from traditional field effect transistor. There is one source and one drain contact as well as a gate to control the current flow.

In contrast to planner MOSFETs the channel between source and drain is build as a three dimensional bar on a top of a silicon substrate , called fin.  The gate electrode is then wrapped around the channel, so that there can be formed several gate electrodes on each side which leads to reduced leakage effects and an enhanced drive current.

low power techniques

We can use the following techniques for a low power design.
1. power gating
2. multiple supply voltages (multi-VDD)
3. voltage scaling.
4.Multi-threshold CMOS (Multi-VT)
5.Adaptive Body-Biasin
6. clock gating

Power Gating: UPF (Unified Power Format)
Power gating is a technique used in integrated circuit design to reduce power consumption by shutting off to blocks of the circuit that are not in use. In addition to reducing stand-by or leakage power , power gating has the benefit of enabling Iddq testing.
The basic purpose of power gating is to temporarily shutting down blocks in a design when the blocks are not in use. This will reduce the leakage power of the chip. Power gating means switching off  an area of a design when its functionality is not require, and then restoring power when it is required. This temporary shutdown time can also called as "low power mode" or "inactive mode", again when we need that particular part of the design in operation then we can turn on the power and that state is called as "active mode".

Switching ON and OFF can be down either by software or hardware control. Th power supply of the entire design is cut off when the circuit is not in use. Such designs do not require data to be retained in the registers or latches used in the design. Functional verification of design is still required to make sure that the position of the designs that are awake function properly and also ensure that the system would work when power is restored in the sleeping part of the device.

When the power is shut off, each power domain must be isolated from rest of the design, so that it does not corrupt the downstream logic.  Power shutdown results in slow output from the power gated blocks. These output spends significant time at threshold voltage, causing large crowbar currents in the always on block, for this purpose we need isolation cells.

Isolation cells are used to prevent these crowbar currents. The isolation cells are placed between the output of the power gated blocks and inputs of the always on blocks.
Lets see the following 2 power domains D1 and D2. D1 is the power shut down domain and D2 is always-on. Now lets say there are a few signals from D1 to D2, suppose at any time if the D1 goes to in-active mode (Switched OFF) and if the signal traversing from D1 to D2 gets some noise or some unwanted signal from some source it can trigger the logic in the D2 domain, which will do unwanted functionality of the circuit, to prevent this Isolation cells are used in between the two domains.

Now if we have isolated the shut down domain from the other domain but we need to retain the last values stored in the registers in the shut down domain for this we use the retention Registers.
Retention Registers:
Retention cells are used in the low power domain to retain the values when the domain power goes into OFF state. these retention registers are special low leakage flip-flops used to hold the data of main register of the power gated block. Thus internal state of the block during power down mode can be retained and loaded back to it when the block is reactivated, retention registers are always powered up. The retention strategy is design dependent. During the power gating data can be retained and transferred back to block when power gating is withdrawn. Power gating controller controls the retention mechanism such as when to save the current contents of the power gating block and when to restore it back.

Level Shifters:
Level shifters are used in such a design where multi voltage supply have been used, now Consider the above two voltage domain D2 and D1 , if there are few signals from D2 (1.0 V) are travelling to D1 0.85V domain, their supply voltage is different then we need to insert level shifter in that domain.

The main function of level shifter is to shift the voltage of the particular domain as per the signal (from which domain it is coming).

Power Switches:
Power switches are used to switch off the power shut domain.

PVT

PVT is acronym for Process-Voltage-Temperature.

PVTs model variations in Process, Voltage and Temperature. There's other term OCV which refers to On-Chip Variation. PVTs model inter-chip variations while OCVs model intra-chip variations. 

Let's talk about PVTs in detail:

1) Process:

You must have heard people talking in terms of process values like 90nm, 65nm, 45nm and other technology nodes. These values are characteristic of any technology and represents the length between the Source and Drain of a MOS transistor . While manufacturing any die, it has been seen that the dies that are present at the center are pretty accurate in their process values. But the ones lying on the periphery tend to deviate from this process value. The deviation is not big, but can have significant impact on timing.


The following formula for current flowing in a MOS transistor:

 L represents the process value. For same temperature and voltage values, current for 45nm process would be more than current for 65nm process.
More is the current, faster is the charging/discharging of capacitors. And this means, delays are less.

2) Voltage:

The voltage that any semiconductor chip works upon is given from outside. Recall while working on breadboards in your labs, you used to connect a 5V supply to the Vcc pin of your IC. Modern chips work on very less voltage than that. Typically around 1V-1.2V.


This voltage must be the output of either a DC source or maybe the output of some voltage regulator. The output voltage of voltage regulator might not be a constant over a period of time. Let's say, you expected your voltage regulator to give 1.2V, but after 4 years, it's voltage dropped down to 1.08V or increased up to 1.32V. So, you gotta make sure your chip is working well between 1.08 and 1.32V!!


This is where the need to model Voltage variations come into picture.
From the same equation as above, it can be seen that more is the voltage, more is the current. And hence, delays are less.

3) Temperature:

The ambient temperature also impacts the timing. Let's say you are working on a gadget in Siachen glacier where temperature can drop down to -40 degrees centigrade in winters and you expect your device to be working fine. Or maybe you are in Sahara desert, where ambient temperature is +50 degrees and your car engine temperature is +150 degrees and again you expect your chip to working fine. While designing, therefore, STA engineers need to make sure that their chip will function correctly in the temperatures between -40 to +150 degrees.



Higher is the temperature, more is the collision rate of electrons within the device. This increased collision rate forbids other electrons in the periphery to move. Since electron movement is responsible for current flowing in the device, current would decrease with increase in temperature. Therefore, delays are normally more at higher temperatures.


For technology nodes below 65nm, there's a phenomenon called TEMPERATURE INVERSION, where delays tend to increase with decreasing temperature. We shall talk about the same later. Don't get confused with it here.

WORST PVT:

Process worst-Voltage min- Temperature-max

BEST PVT:

Process best-Voltage max- Temperature-min

WORST COLD PVT:

Process worst-Voltage min-Temperature min

BEST HOT:

Process best-Voltage max-Temperature max