Power Gating

Power Gating is a technique used in integrated circuit design to reduce power consumption, by shutting off the current to blocks of the circuit that are not is use.

 Power gating is used to save the leakage power when the system is not in operation. This is accomplished by adding a switch either to VDD or VSS supply. When the design is power gated it literally means the block is powered OFF. Powering OFF a design block is the most beneficial technique of all the low power techniques because you dissipate near zero power. Near zero because the switching circuit used for implementing power gating still dissipate leakage power even in power gating mode. The control to the power gating switching circuit is generated by the Power gating control block.

When VDD is gated the power switch is called the “header” switch. Similarly if VSS is gated we call it as “footer” switch. To gate VDD we use PMOS transistor where as to gate VSS we use NMOS transistor. In reality a single switch is not sufficient to power the whole design. Hence many parallel switches are implemented to achieve low voltage ramp up time and avoid other IR drop issues.

Effect of Power Gating:

                    Consider a situation where header switch is turned OFF. It means the VDD supply is cut off to the power gated block. But VSS is still active. VSS tries to pull the circuit elements to VSS voltage but after a certain period of time the voltage level of the circuit reaches equilibrium and it stays at an intermediate voltage which is above the VSS voltage level. Similarly when VSS is turned OFF the voltage level of the power gated block reaches a constant intermediate value above VSS. Typically these intermediate voltage values are near to the threshold voltages of the CMOS transistors. When such voltage level signals are feed as an input to the powered up domain the circuits spends more time in threshold voltage level there by causing crow bar currents. This is the reason behind the usage of Isolation cells for the output signals of the powered down block.

Types of power gating:

                   Based on the scale on which the power gating is applied it can be of two types,

• Fine grain power gating
• Coarse grain power gating

                  Fine grain power gating uses a power a a A power switch in each of the standard cell to gate the power to the cell. Obviously the area penalty of such an implementation is very huge. Hence fine grain power gating is least preferred option. Also when a particular cell is power gated the output of the cell need to be isolated from other non-power gated cells. Because of such reasons designers prefer coarse grain power gating over fine grain.

                In Coarse grain power gating the power is gated over a region of design (usually classified as a power domain). Because of this the area penalty is relatively very less compared to the fine grain power gating. Also the outputs of the power domain can be isolated relatively easier than isolating every cell as in fine grain power gating. Some of the challenges of coarse grain power gating are minimizing the power up ramp time and manage the IR drop. This is because careful design of parallel switches is required to drive the entire power grid of power gated block.

Factors Influencing Power Switch Network Design:

                    The factors which are to be considered while designing power switch network are,

• Rush current
• Leakage current
• IR drop
• Ramp up time

Rush Current: Rush current is the current drawn by the circuit during initial power up. When an electrical load is powered up it draws a huge current initially to charge up its internal capacitors. This current is many times the average current consumed by the electrical component during its normal operation. For any electrical component there is a limit to the amount of current a component can withstand. In silicon a power domain is like an electrical load to the power switch network. When a power domain is powered up from shutdown all the capacitors in the power domain starts to charge. Since all the capacitors starts to charge simultaneously the amount of charge drawn is huge which cause a sudden rush of current. This rush current can damage the power switch network. Hence we need a careful design of power switch network to mitigate the effect of rush current. Usually many parallel power switches are implemented by dividing the power domain supply grid into many small blocks each block powered by one or more power switches. By doing so the load on each of the power switch is reduced considerably and rush current can be minimized.

Leakage Current: Like any other CMOS transistor power switch also has some leakage current. The number of power switches used to implement the power switch network should be optimal. By having more power switches than required contributes to the leakage current of the power switching network. Usually the power switches are implemented by using High VT cells (MTCMOS).

IR Drop: To handle rush currents the power switches or sleep transistors are designed with high channel resistance. But this leads to IR drop across the power switch thereby degrading the actual logic cells functionality. So the power switch network should be designed to minimize the IR drop across the power switches. To solve this issue designers use two types of power switches one which is used during power up to handle the rush current and then the second one during normal operation. This type of switches are called mother and daughter type switches. The control inputs to these types of power switches are controlled such that one is active at a time.

Ramp Up Time: The time required for powering up a shut down power domain is called ramp up time. This ramp up time should be as minimum as possible. The power network design should be done such a way that the ramp up time is less which is usually done by increasing the number of power switches or sleep transistors.