Now it's time to discuss the practical implementation of setup and hold time, means in a circuit.
- How will you calculate the setup and hold values?
- How will you analyze setup and hold violation in a circuit?
- If you have to improve timing of a circuit then what can you do?
There are few formulas to calculate different parameter. First we will solve few examples which will give you an basic idea about these formulas, then in the last we will summarize all those in one place.
We saw a lot of confusion with respect to setup and hold timing calculation. Actually there are two things.
- Timing specification of a Block/Circuit/Library:
- You have a block with input A and output Y. Some combinational logic is there between A and Y.
Now you have to calculate following parameters for that block
- Setup Time Value at Input A
- Hold time value at Input A
- Maximum operating clock frequency or Time Period for that block.
- Clock to Y delay value
- Input A to output Y delay value
- Timing Violation of a Circuit
- You have to operate a circuit at a particular clock frequency and now you have to find out whether this circuit has any setup or hold violation.
So in second case all the parameters are given and you have to find out whether this circuit has any violation or not and in first case you have to find out all the parameters keeping in mind that there should not be any violation.
Let's discuss in reverse order.
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Problem1: In the following circuit, Find out whether there is any Setup or Hold violation?
Solution:
Hold Analysis:
When a hold check is performed, we have to consider two things-
- Minimum delay along the data path
- Maximum delay along the clock path
If the difference between the data path and the clock path is negative, then a timing violation has occurred. (Note: There are few exceptions for this- we will discuss this some other time)
Data Path is : CLK --> FF1/CLK --> FF1/Q --> inverter --> FF2/D
Delay in data Path
=min(wire delay to the clock input of FF1) + min(CLK-to-Q delay of FF1) + min(cell delay of inverter) + min( 2 wire delay - "Q of FF1-to-inverter" and "inveter-to-D of FF2")
=Td =1+9+6+(1+1)= 18ns
Clock Path is: CLK --> Buffer -->FF2/CLK
Clock Path Delay
=max(wire delay from CLK to Buffer Input) + max(cell delay of buffer) + max(wire delay from buffer output to FF2/CLK pin) + (hold time of FF2)
=Tclk = 3 +9+3+2 = 17ns
Hold Slack = Td - Tclk = 18ns - 17ns = 1 ns
Since Hold Slack is Positive --> No Hold Violation.
Note: If the hold time had been 4ns instead of 2ns, then there would have been a hold violation.
Td = 18ns and Tclk = 3+9+3+4 = 19ns
so hold Slack = Td -Tclk = 18ns -19ns = -1ns
Setup Analysis:
When a setup check is performed, we have to consider two things-
- Maximum delay along the data path
- Minimum delay along the clock path
If the difference between the clock path and data path is negative, then a timing violation has occurred. (Note: There are few exceptions for this- we will discuss this some other time)
Data Path is: CLK-->FF1/CLK-->FF1/Q-->inverter-->FF2/D
Delay in data Path:
=max(wire delay to the clock input of FF1) + max(Clk-to-Q delay of FF1) + max(cell delay of inverter) + max(2 wire delay - "Q of FF1-to-inverter" and "inverter-to-D of FF2")
=Td = 2+11+9+(2+2)=26ns
Note: The first part of the clock path delay (during setup calculation) is the clock period, which has been set to 15ns. Hope you remember in last blog. We have mentioned very clearly that Setup is checked at the next clock cycle. That is the reason for clock path delay we have to include the clock period also.
Clk Path is: CLK-->Buffer -->FF2/CLK
Clock Path Delay
= (clock period) + min(wire delay from CLK to Buffer Input) + min(cell delay of Buffer) + min(wire delay from buffer output to FF2/CLK pin) - (Setup of FF2)
=Tclk = 15+2+5+2-4=20ns
Setup Slack = Tclk - Td = 20ns - 26ns = -6ns
Since Setup Slack is negative , --> Setup Violation.
Note: A bigger clock period or a less maximum delay of the inverter solve this setup violations in the circuit.
E.g
If clock period is 22ns , then
Tclk = 22+2+5+2-4=31-4=27ns and Td = 26ns
Setup Slack = Tclk - Td = 27 - 26 = 1 ns ( no violation)
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Problem2: In order to work correctly, what should be the setup and hold time at Input A in the following circuit. Also find out the maximum operating frequency for this circuit. (Note: Ignore Wire Delay). Where Tsu- setup time; Thd- hold time ; Tc2q- Clock-2-Q delay.
Solution:
Step1: Find Out the maximum Register to register Delay.
Max Register to Register Delay
=(clk-to-Q delay of U2 ) + (Cell Delay of U3) + (all wire delay ) + ( setup time of U1)
= 5 + 8 + 3 = 16 ns
Note:
There are 2 register to register paths
- U2 -->U3-->U1 (delay = 5+8+3= 16ns)
- U1 -->U4-->U2 (delay = 5+7+3=15ns )
- we have to pick maximum one.
Step2: Find Out Setup Time:
A Setup Time = Setup time of FlipFlop + Max (Data Path Delay) - Min (clock path delay)
= （Setup Time of Flipflop + A2D Max Delay ) - (Clk Path Min Delay)
= Tsu + (Tpd U7 +Tpd U3 + Wire Delay ) - Tpd U8
= 3 + (1+8) - 2 = 10ns
Note:
- Here we are not using the clock period. Because we are not suppose to calculate the Setup violation. We are calculating Setup time.
- All the wire delay is neglected. If wire delay present, we have to consider those one.
- There are 2 data path
- A-->U7-->U4-->D of U2 (Data Path Delay = 1+7 = 8ns )
- A-->U7-->U3-->D of U1 (Data Path Delay = 1+8 =9ns )
- Since for Setup calculation we need maximum data path delay, we have choose 2nd for calculation.
Step3: Find Out Hold Time:
A Hold Time = Hold Time of FlipFlop + max (clock path delay ) -min (data path delay)
= (hold time of flipflop + clock path max delay ) - (A2D max delay)
= Thd + Tpd U8 - (Tpd U7 + Tpd U4 + Wire Delay )
= 4 + 2 - ( 1 + 7) = -2 ns
Note: Same explanation as for setup time. For hold time we need minimum data path, so we have picked the first data path.
Step4: Find out clock to out time.
clock to out
= cell delay of U8+ Clk-to-Q delay of Flipflop+ cell delay of U5+ cell delay of U6 + (all wire delay)
= Tpd U8 + U2 Tc2q + U5 Tpd + U6 Tpd
= 2 + 5 + 9 +6 = 22 ns
Note:
- There are 2 clock to out path - one from flipflop U1 and other from U2
- Since in this case the CLK-to-Q path for both flipflop is same, we can consider any path. But in some other circuit where the delay is different for both the paths, we should consider the max path delay.
Step5: Find Pin to Pin combinational Delay (A to Y Delay)
Pin to Pin combinational Delay (A to Y)
= U7 Tpd + U5 Tpd + U6 Tpd
= 1 + 9 + 6 = 16ns
Step6 : Find Out Max Clock Frquemcy:
Max Clock Fren = 1/Max (Reg2reg, Clk2out, Pin2pin)
= 1/Max ( 16, 22, 16)
= 45.5 Mhz
So summary is:
Parameter Description Min Max Units
Tclk clock period 22 ns
Fclk clock Frquency 45.5 Mhz
Atsu A setup time 10 ns
Athd A Hold Time -2 ns
A2Y A to Y Tpd 16 ns
Ck2Y Clock to Y Tpd 22 ns
Note: Negative Hold Time are typically specified as 0 ns
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Problem3: In the above circuit, Try to improve the timing by adding any "Buffer" or "Register".
Solution:
Best way of doing this is "Register of all input and Output." We are adding DFF so same specification (as U2 and U1).
