setup and hold time violations

Few important things to note down here -
-- Data is launched from FF1/D to FF1/Q at the positive clock edge at FF1/C.
-- At FF2/D,  input data is coming from FF1/Q through a conbinational logic.
-- Data is capturing at FF/D, at the positive clock edge at FF2/C
-- So I can say that launching flip-flop is FF1 and capturing flip-flop is FF2.
-- So data path is FF1/C --> FF1/Q --> FF2/D
-- For a single cycle circuit, Signal has to be propagate through data path in one clock cycle. Means if    data is launched at time = 0ns from FF1 then it should be captured at time = 10 ns  by FF2.
So for setup analysis at FF2, data should be stable "Ts" time before the positive edge at FF2/C. Where     "Ts" time is the setup time of FF2.
-- If  Ts = 0ns, then, data launched from FF1 at time = 0ns should arrive at D of FF2 before or at time
   = 10ns. If data takes too long ( greater than 10ns) to arrive ( means it is not stable before clock edge
   at FF2), it is reported as setup violation.
    If Ts = 1 ns, then, data launched from FF1 at time = 0ns should arrive at D of FF2 before or at            time = (10ns - 1ns) = 9ns . If data takes too long (greater than 9ns) to arrive ( means it is not stable
   before 1 ns of clock edge at FF2), it is reported as setup violation.

For hold analysis at FF2, data should be stable "Th" time after the positive edge at FF2/C, where "Th" is the hold time of FF2. Means there should not be any change in the input data at FF2/D between positive edge of clock at FF2 at Time = 10ns and Time = 10ns + Th.
-- To satisfy the hold condition at FF2 for the data launched at FF1 at 0ns, the data launched by FF1 at 10ns should not reach at FF2/D before 10ns + Th.
-- If Th = 0.5 ns, then we can say that the data launched from FF1 at time 10ns does not get propagated so soon that it reaches at FF2 before time (10+0.5) = 10.5ns ( or say it should reach from FF1 to FF2 with in 0.5ns ). If data arrive so soon ( means with in 0.5ns from FF1 to FF2, data can't be stable at FF2 for time = 0.5ns after the clock edge at FF2), its reported Hold violation.

With above explanation, there is 2 important things;
1. Setup is checked at next clock edge.
2. Hold is checked at same clock edge.

Setup check timing can be more clear for the above flip-flop combination with the help of following explanation.

In the above fig you can see that data launched at FF1/D ( at launch edge) reaches at FF2/D after a specific delay ( CLK-to-Q delay + Combinational Logic Delay) well before the setup time requirement of Flip-Flop FF2, so there is no setup violation.
From the fig its clear that if Slack = Required Time - Arrival Time < 0 (-ive) , then there is a setup violation at FF2.

Hold Check Timing can be more clear with the help of following circuit and explanation.

In the above fig you can see that there is a delay in the CLK and CLKB because of delay introduced by the serious of buffer  in the clock path. Now flip-flop FF2 has a hold requirement and as per that data should be constant after the capture edge of CLKB at Flip-Flop FF2.
You can see that desired data which suppose to capture by CLKB at FF2.D should be at Zero (0) logic state and be constant long enough after the CLKB capture edge to meet hold requirement but because of very short of logic delay between FF1/Q and FF1/D, the change in the FF1/Q propagates very soon. As a result of that there occurs a Hold violations.
This type of violation (hold violation)can be fixed by shorting the delay in the clock line or by increasing the delay in the data path.

Setup and Hold violation calculation for the single clock cycle path is very easy to understand. But the complexity increases in case of multi-cycle path, Gated clock, flip-flop using different clocks, latches in place of Flip-Flop.