\Noise:
The term “noise” in electronic design generally means any undesirable deviation in voltage of a net that ought to have a constant voltage, such as a power supply or ground line. In CMOS circuits, this includes data signals being held constant at logic 1 or logic 0.
For noise analysis tool considers the cross-coupling between aggressor nets and victim nets.
it determines the worst-case noise bump or glitch on steady-state victim net.
Steady-state means that the net is constant at logic 1 or logic 0.
The main commands for noise analysis are the check_noise, update_noise, and report_noise commands, which operate in a manner similar to the check_timing, update_timing, and report_timing
Prime time gives the noise reports as
1.Above high
2.Above Low
3.Below Low
4. Below high
There are many different causes of noise such as charge storage effects at p-n junctions, power supply noise, and substrate noise. However, the dominant noise effect in deep-submicron CMOS circuits is crosstalk noise
Crosstalk delay: Crosstalk delay is same as noise but in this case both the nets are not in a steady state.
there is some transition happening on both the nets.
crosstalk delay depends on the propagating direction of the aggressor and victim nets which makes the transition slower or faster.
Note: for setup analysis tool add crosstalk delay to the timing path and for hold it subtract the delta delay from the cell delay.
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