Clock Tree Synthesis CTS

What is CTS?

• Process of balancing clock skew and Minimizing Insertion Delay in order to meet timing , power requirements and other requirements.
• Process of distributing clock signal to clock pins based on physical information.
•  Clock Buffer Tree is build to achieve the CTS goals.

CTS Goals:

• Meet CTS design rule constraints such as Maximum Transition Delay, Maximum Load Capacitance, Maximum Fanout,  Maximum Buffer Levels.
• Meet the clock tree targets such as Maximum skew, Min/Max Insertion Delay.

Checklist before Clock Tree Synthesis:

• The design is placed and optimized
• Power and Ground nets are pre-routed
• Acceptable Congestion
• Meet Timing Constraints (~0ns Slack)
• No DRC Violations Such as Max Tran, Max Cap
• High Fanout Nets (Reset , Enable Pins are synthesized with buffers)

How to check whether Design is ready for CTS or not?

check_physical_design -for_cts:

1. checks design placed or not

2. checks all clocks are defined or not

3.checks for clock roots are not hierarchical pins

check_clock_tree:

checks and warns if:

1. A clock source pin is hierarchical pin  

2. There are multiple clocks per Register

3. A clock tree has no synchronous pin

4. A generated clock with improperly specified Master clock.

MCMM: Multi-Corner Multi-Mod

What's MCMM

MCMM stands for: Multi-Corner Multi-Mode (static timing analysis )

What's a Mode

A mode is defined by a set of clocks, supply voltages, timing constraints, and libraries. It can also have annotation data, such as SDF or parasitics files.


Many chip have multiple modes such as functional modes, test mode, sleep mode, and etc.

What's a Corner

A corner is defined as a set of libraries characterized for process, voltage, and temperature variations.


Corners are not dependent on functional settings; they are meant to capture variations in the manufacturing process, along with expected variations in the voltage and temperature of the environment in which the chip will operate.

Example:

Multi-mode multi-corner (MMMC) analysis refers to performing STA across multiple operating modes, PVT corners and parasitic interconnect corners at the same time. For example, consider a DUA that has four operating modes (Normal, Sleep, Scan shift, Jtag), and is being analyzed at three PVT corners (WCS, BCF, WCL) and three parasitic interconnect corners (Typical, Min C, Min RC)

 

There are a total of thirty six possible scenarios at which all timing checks, such as setup, hold, slew, and clock gating checks can be performed. Running STA for all thirty six scenarios at the same time can be prohibitive in terms of runtime depending upon the size of the design. It is possible that a scenario may not be necessary as it may be included within another scenario, or a scenario may not be required. For example, the designer may determine
that scenarios 4, 6, 7 and 9 are not relevant and thus are not required. Also, it may not be necessary to run all modes in one corner, such as Scan shift or Jtag modes may not be needed in scenario 5. STA could be run on a single scenario or on multiple scenarios concurrently if multi-mode multicorner capability is available.

Congestion

Congestion needs to be analyzed after placement and the routing results depend on how congested your design is. Routing congestion may be localized. Some of the things that you can do to make sure routing is hassle free are:

Placement blockages: 

The utilization constraint is not a hard rule, and if you want to specifically avoid placement in certain areas, use placement blockages.
Soft blockages (buffer only)
Hard blockages (No std cells and buffers are allowed to Place)
Partial blockages (same as density screens)
Halo (same as soft blockage but blockage can also be moved w.r.t Macro.)

Macro-padding:

 Macro padding or placement halos around the macros are placement blockages around the edge of the macros. This makes sure that no standard cells are placed near the pin outs of the macros, thereby giving extra breathing space for the macro pin connections to standard cells.

Cell padding:

Cell Padding refers to placement clearance applied to std cells in PnR tools. This is typically done to ease placement congestion or reserve some space for future use down the flow.
For example typically people apply cell padding to the buffers/inverters used to build clock tree, so that space is reserved to insert DECAP cells near them after CTS.

Cell padding adds hard constraints to placement. The constraints are honored by cell legalization, CTS, and timing optimization, unless the padding is reset after placement so
those operations can use the reserved space. You can use cell padding to reserve space for routing.

The command "specifyCellPad" is used to specify the cell padding in SOC-Encounter.

This command adds padding on the right side of library cells during placement.

The padding is specified in terms of a factor that is applied to the metal2 pitch. For example, if you specify a factor of 2, the software ensures that there is additional clearance of two times the metal2 pitch on the right side of the specified cells.

Maximum Utilization constraint (density screens): 

Some tools let you specify maximum core utilization numbers for specific regions. If any region has routing congestion, utilization there can be reduced, thus freeing up more area for routing.
each tool is having this setting, check wityh your DA for the detail.

set_congestion_options -max_util .6 -coordinate {10 20 40 40}