Clock Tree Synthesis CTS

What is CTS?

• Process of balancing clock skew and Minimizing Insertion Delay in order to meet timing , power requirements and other requirements.
• Process of distributing clock signal to clock pins based on physical information.
•  Clock Buffer Tree is build to achieve the CTS goals.

CTS Goals:

• Meet CTS design rule constraints such as Maximum Transition Delay, Maximum Load Capacitance, Maximum Fanout,  Maximum Buffer Levels.
• Meet the clock tree targets such as Maximum skew, Min/Max Insertion Delay.

Checklist before Clock Tree Synthesis:

• The design is placed and optimized
• Power and Ground nets are pre-routed
• Acceptable Congestion
• Meet Timing Constraints (~0ns Slack)
• No DRC Violations Such as Max Tran, Max Cap
• High Fanout Nets (Reset , Enable Pins are synthesized with buffers)

How to check whether Design is ready for CTS or not?

check_physical_design -for_cts:

1. checks design placed or not

2. checks all clocks are defined or not

3.checks for clock roots are not hierarchical pins

check_clock_tree:

checks and warns if:

1. A clock source pin is hierarchical pin  

2. There are multiple clocks per Register

3. A clock tree has no synchronous pin

4. A generated clock with improperly specified Master clock.