Maximum Clock Frequency

As we know that now a day all the chips has combinational   + sequential circuit. So before we move forward, we should know the definition of "Propagation delay" in both type of circuits.

Propagation Delay in the combinational circuits:
Let's consider a "NOT" gate and input/output waveform as shown in the figure,

From the above figure,

- Rise Time(tr): the time required for a single to transition from 10% of its maximum value to 90% of its maximum value.
- Fall Time(tf): the time required for a single to transition from 90% of its maximum value to 10% of
 its maximum value.
- Propagation Delay (tpLH, tpHL) The delay measured from the time the input is at 50% of its full swing value to the time the output reaches its 50% value.

We want to rephrase above mention definition as:
- This value indicates the amount of time needed to reflect a permanent change at an output, if there is any change in logic of input.
- Combinational logic is guaranteed not to show any further output changes in response to input changes after tpLH or tpHL time units have passed.
So, when an input X change, the output Y is not going to change instantaneous. Inverter output is going to maintain its initial value for some time and then its going to change from it's initial value.
After the propagation delay (tpLH or tpHL -- depends on what type of change -- low to high or high to low) , the inverter output is stable and is guaranteed not to change again until another input change (here we are not considering any SI/noise effect).

Propagation Delay in the sequential circuits:
In the sequential circuits, timing characteristics are with respect to the clock input. You can correlate it in this way that in the combinational circuit every timing characteristic/parameter are with respect to the data input change but in the sequential circuits the change in the "data input" is important but change in the clock value has higher precedence. E.g. in a positive-edge-triggered flip-flop, the output value will change only after a presence of positive-edge of clock whether the input data has changed long time ago.
so flip-flops only change value in response to a change in the clock value, timing parameters can be specified in relation to the rising (for positive edge-triggered ) or falling (for negative edge-triggered) clock edge.

Let's consider the positive edge flip-flop as shown in fig,

Propagation delay , tpHL and tpLH, has the same meaning as in combinational circuit - beware propagation delays usually will not be equal for all input to output pairs.

setup time (tsu) - this value indicates the amount of time before the clock edge that date input D must be stabel.
Hold Time(th) - this value indicates the amount of time after the clock edge that data input D must be held stable.
The circuit must be designed so that the D flip-flop input signal arrives at least "tsu" time units before the clock edge and does not change until at least "th" time units after the clock edge. If either of these restrictions are violated for any of the flip-flops in the circuit, the circuit will not operate correctly. These restrictions limit the maximum clock frequency at which the circuit can operate.

The maximum clock frequency for a circuit:

now let's understand the flow of data across these flip-flops.

- Let's assume data is already present at D of flip-flop A and it's in the stable form.

- Now clock pin of FF (flip-flop)A , i.e Clk has been triggered with a positive clock edge (low to high) at time "0ns".

- As per the propagation delay of the sequential circuit (tclk->Q), it will take at least 10ns for a valid output data at the pin X.

       -- Remember -- If you will capture the output before 10ns, then no one can give you the guarantee for the accurate/valid value at the pin X.

- This data is going to transfer through the inverter F. Since the propagation delay of "F" is 5ns, it means, you can notice the valid output at the pin Y only after 10ns+5ns = 15ns ( with reference to the positive clock edge - 10ns of FF A and 5 ns of  inverter).

       -- Practically this is the place where a more complex combinational circuit are present between 2 FFs. So in a more compext design, if a single path is present between X and Y,  then the total time taken by the data to travel from X to Y is equal to the sum of the propagation delay of all the combinational circuits/devices. 

- Now once valid data reaches at the pin Y , then this data supposed to capture by FF B at the next clock positive edge ( in a single cycle circuit).

      -- we generally try to design all the circuit in such a way that it operates in a single clock cycle. 

- For properly capturing the data at FF B, data should be present and stable 2 ns (setup time) before the next clock edge as part of setup definition.

So it means between 2 consecutive positive clock edge, there should be minimum time difference of 10ns + 5ns + 2ns = 17ns . And we can say that for this circuit the minimum clock period should be 17ns. ( if we want to operate the circuit in single clock cycle and accurately).

Now we can generalize  this

minimum clock period = tclk-Q (A) + tpd (F) + ts(B)

And "Maximum Clock Frequency = 1/(Min clock period)"