FinFET Technology

A multigate device or multiple gate field-effect transistor (MuGFET) refers to a MOSFET (metal-oxide-semiconductor field effect transistor) which incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate , or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a Multiple Independent Gate Field Effect Transistor (MIGFET).

General MOSFET at submicron level is suffering from several submicron issues like short channel effects, threshold voltage variation etc. FinFET is supposed to overcome the short channel effects. Structure of of FinFET is shown in below,

Silicon on insulator (SOI) process is used to fabricate FinFET.  This process insures the ultra thin specifications of device regions. in FinFET electrical potential throughout the channel is controlled by the gate voltage. This is possible due to the proximity of gate control electrode to the current conduction path between source and drain. These characteristics of the FinFET minimize the short channel effect. Advantages of the FinFET over its bulk-si counterpart are as follows:
Conventional MOSFET manufacturing processes can also be used to fabricate FinFET.
FinFET provides better area efficiency compared to MOSFET.
mobiblity of the carriers can be improved by using FinFET process in conjunction with the strained silicon process.
FinFET device structure Silicon on Insulator (SOI) process is used to manufacture FinFET.  A single poly silicon layer is deposited over a fin. Thus poly silicon straddles the fin structure to form perfectly aligned gates. Here a fin itself acts as a channel and it terminates on both sides of source and drain.  In general MOSFET device, over the si substrate poly silicon gate is formed. Poly silicon gate controls the channel.  Straddling of poly silicon gate over the Si fin gives efficient gate controlled characteristics compared to MOSFET.  Since gate straddles the fin the length of the channel is same as that of width of the fin. As there are two gates effectively around the fin we can write, width of the channel is equivalent to twice the height of the fin i.e. w=2*h. A term called *fin pitch* is used to define the space between two fins. Height of the FinFET is equivalent to width of the MOSET.  If w is the fin pitch then to attain same area efficiency required fin height is w/2. But practical experiments have shown that fin height can be greater than w/2 for a fin pitch of w. thus FinFET achieves more area efficiency than MOSFET.

The basic electrical layout and the mode of operation of a FinFET does not differ from traditional field effect transistor. There is one source and one drain contact as well as a gate to control the current flow.

In contrast to planner MOSFETs the channel between source and drain is build as a three dimensional bar on a top of a silicon substrate , called fin.  The gate electrode is then wrapped around the channel, so that there can be formed several gate electrodes on each side which leads to reduced leakage effects and an enhanced drive current.

low power techniques

We can use the following techniques for a low power design.
1. power gating
2. multiple supply voltages (multi-VDD)
3. voltage scaling.
4.Multi-threshold CMOS (Multi-VT)
5.Adaptive Body-Biasin
6. clock gating

Power Gating: UPF (Unified Power Format)
Power gating is a technique used in integrated circuit design to reduce power consumption by shutting off to blocks of the circuit that are not in use. In addition to reducing stand-by or leakage power , power gating has the benefit of enabling Iddq testing.
The basic purpose of power gating is to temporarily shutting down blocks in a design when the blocks are not in use. This will reduce the leakage power of the chip. Power gating means switching off  an area of a design when its functionality is not require, and then restoring power when it is required. This temporary shutdown time can also called as "low power mode" or "inactive mode", again when we need that particular part of the design in operation then we can turn on the power and that state is called as "active mode".

Switching ON and OFF can be down either by software or hardware control. Th power supply of the entire design is cut off when the circuit is not in use. Such designs do not require data to be retained in the registers or latches used in the design. Functional verification of design is still required to make sure that the position of the designs that are awake function properly and also ensure that the system would work when power is restored in the sleeping part of the device.

When the power is shut off, each power domain must be isolated from rest of the design, so that it does not corrupt the downstream logic.  Power shutdown results in slow output from the power gated blocks. These output spends significant time at threshold voltage, causing large crowbar currents in the always on block, for this purpose we need isolation cells.

Isolation cells are used to prevent these crowbar currents. The isolation cells are placed between the output of the power gated blocks and inputs of the always on blocks.
Lets see the following 2 power domains D1 and D2. D1 is the power shut down domain and D2 is always-on. Now lets say there are a few signals from D1 to D2, suppose at any time if the D1 goes to in-active mode (Switched OFF) and if the signal traversing from D1 to D2 gets some noise or some unwanted signal from some source it can trigger the logic in the D2 domain, which will do unwanted functionality of the circuit, to prevent this Isolation cells are used in between the two domains.

Now if we have isolated the shut down domain from the other domain but we need to retain the last values stored in the registers in the shut down domain for this we use the retention Registers.
Retention Registers:
Retention cells are used in the low power domain to retain the values when the domain power goes into OFF state. these retention registers are special low leakage flip-flops used to hold the data of main register of the power gated block. Thus internal state of the block during power down mode can be retained and loaded back to it when the block is reactivated, retention registers are always powered up. The retention strategy is design dependent. During the power gating data can be retained and transferred back to block when power gating is withdrawn. Power gating controller controls the retention mechanism such as when to save the current contents of the power gating block and when to restore it back.

Level Shifters:
Level shifters are used in such a design where multi voltage supply have been used, now Consider the above two voltage domain D2 and D1 , if there are few signals from D2 (1.0 V) are travelling to D1 0.85V domain, their supply voltage is different then we need to insert level shifter in that domain.

The main function of level shifter is to shift the voltage of the particular domain as per the signal (from which domain it is coming).

Power Switches:
Power switches are used to switch off the power shut domain.

PVT

PVT is acronym for Process-Voltage-Temperature.

PVTs model variations in Process, Voltage and Temperature. There's other term OCV which refers to On-Chip Variation. PVTs model inter-chip variations while OCVs model intra-chip variations. 

Let's talk about PVTs in detail:

1) Process:

You must have heard people talking in terms of process values like 90nm, 65nm, 45nm and other technology nodes. These values are characteristic of any technology and represents the length between the Source and Drain of a MOS transistor . While manufacturing any die, it has been seen that the dies that are present at the center are pretty accurate in their process values. But the ones lying on the periphery tend to deviate from this process value. The deviation is not big, but can have significant impact on timing.


The following formula for current flowing in a MOS transistor:

 L represents the process value. For same temperature and voltage values, current for 45nm process would be more than current for 65nm process.
More is the current, faster is the charging/discharging of capacitors. And this means, delays are less.

2) Voltage:

The voltage that any semiconductor chip works upon is given from outside. Recall while working on breadboards in your labs, you used to connect a 5V supply to the Vcc pin of your IC. Modern chips work on very less voltage than that. Typically around 1V-1.2V.


This voltage must be the output of either a DC source or maybe the output of some voltage regulator. The output voltage of voltage regulator might not be a constant over a period of time. Let's say, you expected your voltage regulator to give 1.2V, but after 4 years, it's voltage dropped down to 1.08V or increased up to 1.32V. So, you gotta make sure your chip is working well between 1.08 and 1.32V!!


This is where the need to model Voltage variations come into picture.
From the same equation as above, it can be seen that more is the voltage, more is the current. And hence, delays are less.

3) Temperature:

The ambient temperature also impacts the timing. Let's say you are working on a gadget in Siachen glacier where temperature can drop down to -40 degrees centigrade in winters and you expect your device to be working fine. Or maybe you are in Sahara desert, where ambient temperature is +50 degrees and your car engine temperature is +150 degrees and again you expect your chip to working fine. While designing, therefore, STA engineers need to make sure that their chip will function correctly in the temperatures between -40 to +150 degrees.



Higher is the temperature, more is the collision rate of electrons within the device. This increased collision rate forbids other electrons in the periphery to move. Since electron movement is responsible for current flowing in the device, current would decrease with increase in temperature. Therefore, delays are normally more at higher temperatures.


For technology nodes below 65nm, there's a phenomenon called TEMPERATURE INVERSION, where delays tend to increase with decreasing temperature. We shall talk about the same later. Don't get confused with it here.

WORST PVT:

Process worst-Voltage min- Temperature-max

BEST PVT:

Process best-Voltage max- Temperature-min

WORST COLD PVT:

Process worst-Voltage min-Temperature min

BEST HOT:

Process best-Voltage max-Temperature max

MCMM: Multi-Corner Multi-Mode

What is MCMM?

MCMM stands for: Multi-Corner Multi-Mode (static timing analysis used in the design of digital ICs)

What's a Mode

A mode is defined by a set of clocks, supply voltages, timing constraints, and libraries. It can also have annotation data, such as SDF or parasitics files.

Many chip have multiple modes such as functional modes, test mode, sleep mode, and etc. 

What's a Corner

A corner is defined as a set of libraries characterized for process, voltage, and temperature variations.

Corners are not dependent on functional settings; they are meant to capture variations in the manufacturing process, along with expected variations in the voltage and temperature of the environment in which the chip will operate.

Example:

Multi-mode multi-corner (MMMC) analysis refers to performing STA across multiple operating modes, PVT corners and parasitic interconnect corners at the same time. For example, consider a DUA that has four operating modes (Normal, Sleep, Scan shift, Jtag), and is being analyzed at three PVT corners (WCS, BCF, WCL) and three parasitic interconnect corners (Typical, Min C, Min RC)

There are a total of thirty six possible scenarios at which all timing checks, such as setup, hold, slew, and clock gating checks can be performed. Running STA for all thirty six scenarios at the same time can be prohibitive in terms of runtime depending upon the size of the design. It is possible that a scenario may not be necessary as it may be included within another scenario, or a scenario may not be required. For example, the designer may determine

that scenarios 4, 6, 7 and 9 are not relevant and thus are not required. Also, it may not be necessary to run all modes in one corner, such as Scan shift or Jtag modes may not be needed in scenario 5. STA could be run on a single scenario or on multiple scenarios concurrently if multi-mode multicorner capability is available.

setup time and hold time

• setup time is the minimum amount of time input (D) must be stable before the clock edge.
• hold time is the minimum amount of time input (D) must be stable after the clock edge.

Both setup and hold time for a flip-flop is specified in the library.

1.1 setup time

• data should be stable before the clock edge
• setup time is the amount of time the synchronous input (D) must show up, and be stable before the capturing edge of clock.
• this is so that the data can be stored successfully in the storage device.
• setup violation can be fixed by either slowing down the clock (increase the period ) or by decreasing the delay of the data path logic.

setup information .lib :

timing () {

                related_pin        : "CK";

                timing_type        : setup_rising;

                fall_constraint(Setup_3_3) {

                     index_1 ("0.000932129,0.0331496,0.146240");

                     index_2 ("0.000932129,0.0331496,0.146240");

                     values ("0.035190,0.035919,0.049386", \

                             "0.047993,0.048403,0.061538", \

                             "0.082503,0.082207,0.094815");

                }

1.2 Hold Time

• data should be stable after the clock edge
• hold time is the amount of time the synchronous input (D) stays long enough after the capturing edge of clock so that the data can be stored successfully in the storage device.
• hold violation can be fixed by increasing the delay of the data path or by decreasing the clock uncertainty (skew) if specified in the design.

Hold Information .lib:

timing () {

              related_pin      : "CK";

              timing_type      : hold_rising;

              fall_constraint(Hold_3_3) {

                   index_1 ("0.000932129,0.0331496,0.146240");

                   index_2 ("0.000932129,0.0331496,0.146240");

                   values ("-0.013960,-0.014316,-0.023648", \

                           "-0.016951,-0.015219,-0.034272", \

                           "0.108006,0.110026,0.090834");

              }

Maximum Clock Frequency

As we know that now a day all the chips has combinational   + sequential circuit. So before we move forward, we should know the definition of "Propagation delay" in both type of circuits.

Propagation Delay in the combinational circuits:
Let's consider a "NOT" gate and input/output waveform as shown in the figure,

From the above figure,

- Rise Time(tr): the time required for a single to transition from 10% of its maximum value to 90% of its maximum value.
- Fall Time(tf): the time required for a single to transition from 90% of its maximum value to 10% of
 its maximum value.
- Propagation Delay (tpLH, tpHL) The delay measured from the time the input is at 50% of its full swing value to the time the output reaches its 50% value.

We want to rephrase above mention definition as:
- This value indicates the amount of time needed to reflect a permanent change at an output, if there is any change in logic of input.
- Combinational logic is guaranteed not to show any further output changes in response to input changes after tpLH or tpHL time units have passed.
So, when an input X change, the output Y is not going to change instantaneous. Inverter output is going to maintain its initial value for some time and then its going to change from it's initial value.
After the propagation delay (tpLH or tpHL -- depends on what type of change -- low to high or high to low) , the inverter output is stable and is guaranteed not to change again until another input change (here we are not considering any SI/noise effect).

Propagation Delay in the sequential circuits:
In the sequential circuits, timing characteristics are with respect to the clock input. You can correlate it in this way that in the combinational circuit every timing characteristic/parameter are with respect to the data input change but in the sequential circuits the change in the "data input" is important but change in the clock value has higher precedence. E.g. in a positive-edge-triggered flip-flop, the output value will change only after a presence of positive-edge of clock whether the input data has changed long time ago.
so flip-flops only change value in response to a change in the clock value, timing parameters can be specified in relation to the rising (for positive edge-triggered ) or falling (for negative edge-triggered) clock edge.

Let's consider the positive edge flip-flop as shown in fig,

Propagation delay , tpHL and tpLH, has the same meaning as in combinational circuit - beware propagation delays usually will not be equal for all input to output pairs.

setup time (tsu) - this value indicates the amount of time before the clock edge that date input D must be stabel.
Hold Time(th) - this value indicates the amount of time after the clock edge that data input D must be held stable.
The circuit must be designed so that the D flip-flop input signal arrives at least "tsu" time units before the clock edge and does not change until at least "th" time units after the clock edge. If either of these restrictions are violated for any of the flip-flops in the circuit, the circuit will not operate correctly. These restrictions limit the maximum clock frequency at which the circuit can operate.

The maximum clock frequency for a circuit:

now let's understand the flow of data across these flip-flops.

- Let's assume data is already present at D of flip-flop A and it's in the stable form.

- Now clock pin of FF (flip-flop)A , i.e Clk has been triggered with a positive clock edge (low to high) at time "0ns".

- As per the propagation delay of the sequential circuit (tclk->Q), it will take at least 10ns for a valid output data at the pin X.

       -- Remember -- If you will capture the output before 10ns, then no one can give you the guarantee for the accurate/valid value at the pin X.

- This data is going to transfer through the inverter F. Since the propagation delay of "F" is 5ns, it means, you can notice the valid output at the pin Y only after 10ns+5ns = 15ns ( with reference to the positive clock edge - 10ns of FF A and 5 ns of  inverter).

       -- Practically this is the place where a more complex combinational circuit are present between 2 FFs. So in a more compext design, if a single path is present between X and Y,  then the total time taken by the data to travel from X to Y is equal to the sum of the propagation delay of all the combinational circuits/devices. 

- Now once valid data reaches at the pin Y , then this data supposed to capture by FF B at the next clock positive edge ( in a single cycle circuit).

      -- we generally try to design all the circuit in such a way that it operates in a single clock cycle. 

- For properly capturing the data at FF B, data should be present and stable 2 ns (setup time) before the next clock edge as part of setup definition.

So it means between 2 consecutive positive clock edge, there should be minimum time difference of 10ns + 5ns + 2ns = 17ns . And we can say that for this circuit the minimum clock period should be 17ns. ( if we want to operate the circuit in single clock cycle and accurately).

Now we can generalize  this

minimum clock period = tclk-Q (A) + tpd (F) + ts(B)

And "Maximum Clock Frequency = 1/(Min clock period)"

What is the diffrence between DRC and DFM ?

DRC - Design Rule Check

This is specified by the technology and foundrys all over the world give out these
rules for a particular technology. These rules have to be satisfied in any design (physically)

DFM - Design For Manufacturing

Its a thing which has been there since the 90nm node. As yield and reliability became important factors, foundrys brought out the DFM, which is making designs reliable and yield high.
These are set of rules , we would say guidelines that cover over the DRC rules. These rules are optional but as we go down the deep submicron technologies, its highly important to follow these DFM rules in order to make sure the product is reliable and yield is maintained high.
Making a design with DRC rules has a high probability that the yield of the design is quite less...
Foundrys specifically recommend all the design companies to follow DFM rules wherever possible... 

It is very important of following points:
Yield
Performance 
and
life time of chip.

DFM is very big issue in VLSI.