2 ways to buffer high fanout nets

High fanout nets can be buffered in one or two below ways. The choice depends on if the buffering need to be balanced or not.

1. Using the optDesign command:

EDI using the optDesign command to correct DRVs and timing violations.
The optDesign command does not fix fanout violations by default. To fix fanout violations during optDesign, do the following:

setOptMode -fixFanoutLoad true
optDesign -preCTS


Setting the -fixFanoutLoad option to true will force timing optimization to correct fanout load violations. This method will fix fanout load violations but will not attempt to balance the buffering.

Note: If fanout violations exist after you run the optDesign command, review the *.fanout file that is generated. The remarks column will list a letter code to indicate why a factor violations was not fixed.


2. Buffering a net using the bufferTreeSynthesis command:

The bufferTreeSynthesis command should be used to fix fanout violations if you require the buffer tree to be balanced. Use the bufferTreeSynthesis options to specify the delay and skew constraints along with other desired constraints.
The difference between the buffer tree built by optDesign and the one built by CTS is whether the tool attempts to balance the skew between the endpoints.
For optDesign, we want the tool to build a tree that produces the best timing even if the tree isn't balanced.  For example, if we had a sink in a high fanout tree that was more timing-critical than the others, we would want optDesign to build a tree that delivered the signal to the timing-critical sink earlier than the other sinks.
For CTS, we want the tool to create a tree that balances skew between all of the sinks.  This is desirable in a clock tree scenario because we typically want to minimize skew between registers as a starting point (though we may employ useful skew techniques later where we task the tool to intentionally skew certain registers to improve timing).
For reset trees,  you can allow the tool to use the built-in buffering algorithm of the optDesign command as a starting point.  If you see timing violations arise because of a timing constraint that enforces that the bits in a bus arrive within a certain window, you can seek to build a balanced tree.  If you need to go that route, you can use bufferTreeSynthesis for buffering.