checking the design and analysis setup

Before you begin a full analysis, it is a good idea  to check the characterisitics of the design such as the hierarchy, library elements, ports, nets, cells ; and the analysis setup parameters such as clocks, wire load models, input delay constraints, and output delay constraints.

The check_timing cmd checks for constraint problems such as undefined clocking, undefined input data arrival times, and undefined output data required times. In addition,  it provides info. about potential problems related to minimum clocks seperation ( for master-slave clocking), ignored timing exceptions, combinational feedback loops, and latch fanout.

When the check_timing cmd finds potential problems, it reports them in the following manner:

Information: Checking  'no_clock'.
Warning: There are 4 register clock pins with no clock.
Information: Checking 'no_input_delay'.
Information: Checking 'unconstrained_endpoints'.
Information: Checking 'generic'.
Information: Checking 'latch_fanout'.
Warning: There are 2 level-sensitive latches which fanout to themselves.
Information: Checking 'loops'.
Warning: There are 6 timing loops in the design.
Information: Checking 'generated_clocks'.

Warnings reported by the check_timing cmd do not necessarily indicate true design problems.
 To obtain more info, you can use a variety of report cmds to get info. about the characteristics of the design and the timing constraints that have been placed on the design.

Use the -no_input_delay option to warn if theare are no clock related delays specified on an input port. If there is no input delay specified on an unclocked input port, the check_timing cmd does not generate warnings.

These are some of the more common report cmds:
1) report_design -- Lists the attributes of the design, including the chosen operating conditions, wire load info, and design rules.
2) report_port     -- Lists the ports and shows port info. such as the direction, pin capacitance, wire capacitance, input delay, output delay, related clock, design rules, and wire load info.
3) report_net       -- Lists the nets and shows net info. such as fanin, fanout, capacitance, wire resistance, number of pins, net attributes, and connections.
4) report_cell      -- Lists the cells used in the design and cell info. such as the library name, input names, output names, net connections, cell area, and cell attributes.
5) report_hierarchy -- Generates a hieratchical list of submodules and leaf_level cells in the current design.
6) report_reference -- Generates a list of hierarchical references, showing for each submodule the reference name, unit area, number of occurrences, total area, and cell attributes.
7) report_lib  -- Generates a report on a specified library showing the time units of the library, capacitance units, wire load info, defined operating conditions, logic trippoint thresholds, and names of library cells.
8) report_clock -- Generates a report on the clocks defined for the design, showing for each clock the name, period, rise and fall times, and timing characteristics such as latency and uncetainty.
9)report_wire_load -- Shows the wire load models set on the current design or on the specified cells.
10) report_path_group  -- Generates a report on the path groups in the design. PT organizes timing paths into groups basen on the conditions at the path endpoints.