constraint checking

After PT determines the timing paths and calculates the path delays, it can check for violations of timing constraints, such as setup and hold constraints.

A setup constraint specifies how much time is necessary for data to be available at the input of a sequential device before the clock edge that captures the data in the device. This constraint enfores a maximum  delay on the data path relative to the clock path.

A hold constraint specifies how much time is necessary for data to be stable at the input of a squential device after the clock edge that captures the data in the device. This constraint enfores a minimum delay on the data path relative to the clock path.

In addition to setup and hold constraints, PT can also check recovery/removal constraints, data-to-data constraints, clock-gating setup/hold constraints, and minimum pulse width for clock signals.