How to fix max transition time violations?

The max transition time is one of the three Design Rules ( max fanout, max transition, max capacitance).

It is much more important than setup/hold timing.
As we all know, in STA, the delay of each std. cells is calculated from looking up the NLDM ( non-linear delay model) tables which is defined in library. These tables are two factors: input transition time, and output load. The result of table is the delay value of cell under certain transition and output load.

If the input transition or output load is out of range is within but not the values in NDLM, interpolation is utilized to calculate.
If the input transition or output load is out of range of NLDM , ext-interpolation is used to calculation. But it is natural the result would be rather in-accurate.

So the STA will be rather in-accurate. Timing analysis is un-believable.
Now, you can understand how important max tran is.
-- one more reason of fixing max transition violation is that bigger transition will result in bigger DC
    power consumption.
-- The margin in 30% of max transition is allowed.
For example, if the constraint of max transition is 1 ns, then 1.3 ns is allowed.