MCMM: Multi-Corner Multi-Mod

What's MCMM

MCMM stands for: Multi-Corner Multi-Mode (static timing analysis )

What's a Mode

A mode is defined by a set of clocks, supply voltages, timing constraints, and libraries. It can also have annotation data, such as SDF or parasitics files.


Many chip have multiple modes such as functional modes, test mode, sleep mode, and etc.

What's a Corner

A corner is defined as a set of libraries characterized for process, voltage, and temperature variations.


Corners are not dependent on functional settings; they are meant to capture variations in the manufacturing process, along with expected variations in the voltage and temperature of the environment in which the chip will operate.

Example:

Multi-mode multi-corner (MMMC) analysis refers to performing STA across multiple operating modes, PVT corners and parasitic interconnect corners at the same time. For example, consider a DUA that has four operating modes (Normal, Sleep, Scan shift, Jtag), and is being analyzed at three PVT corners (WCS, BCF, WCL) and three parasitic interconnect corners (Typical, Min C, Min RC)

 

There are a total of thirty six possible scenarios at which all timing checks, such as setup, hold, slew, and clock gating checks can be performed. Running STA for all thirty six scenarios at the same time can be prohibitive in terms of runtime depending upon the size of the design. It is possible that a scenario may not be necessary as it may be included within another scenario, or a scenario may not be required. For example, the designer may determine
that scenarios 4, 6, 7 and 9 are not relevant and thus are not required. Also, it may not be necessary to run all modes in one corner, such as Scan shift or Jtag modes may not be needed in scenario 5. STA could be run on a single scenario or on multiple scenarios concurrently if multi-mode multicorner capability is available.

MCMM: Multi-Corner Multi-Mode

What is MCMM?

MCMM stands for: Multi-Corner Multi-Mode (static timing analysis used in the design of digital ICs)

What's a Mode

A mode is defined by a set of clocks, supply voltages, timing constraints, and libraries. It can also have annotation data, such as SDF or parasitics files.

Many chip have multiple modes such as functional modes, test mode, sleep mode, and etc. 

What's a Corner

A corner is defined as a set of libraries characterized for process, voltage, and temperature variations.

Corners are not dependent on functional settings; they are meant to capture variations in the manufacturing process, along with expected variations in the voltage and temperature of the environment in which the chip will operate.

Example:

Multi-mode multi-corner (MMMC) analysis refers to performing STA across multiple operating modes, PVT corners and parasitic interconnect corners at the same time. For example, consider a DUA that has four operating modes (Normal, Sleep, Scan shift, Jtag), and is being analyzed at three PVT corners (WCS, BCF, WCL) and three parasitic interconnect corners (Typical, Min C, Min RC)

There are a total of thirty six possible scenarios at which all timing checks, such as setup, hold, slew, and clock gating checks can be performed. Running STA for all thirty six scenarios at the same time can be prohibitive in terms of runtime depending upon the size of the design. It is possible that a scenario may not be necessary as it may be included within another scenario, or a scenario may not be required. For example, the designer may determine

that scenarios 4, 6, 7 and 9 are not relevant and thus are not required. Also, it may not be necessary to run all modes in one corner, such as Scan shift or Jtag modes may not be needed in scenario 5. STA could be run on a single scenario or on multiple scenarios concurrently if multi-mode multicorner capability is available.

setup time and hold time

• setup time is the minimum amount of time input (D) must be stable before the clock edge.
• hold time is the minimum amount of time input (D) must be stable after the clock edge.

Both setup and hold time for a flip-flop is specified in the library.

1.1 setup time

• data should be stable before the clock edge
• setup time is the amount of time the synchronous input (D) must show up, and be stable before the capturing edge of clock.
• this is so that the data can be stored successfully in the storage device.
• setup violation can be fixed by either slowing down the clock (increase the period ) or by decreasing the delay of the data path logic.

setup information .lib :

timing () {

                related_pin        : "CK";

                timing_type        : setup_rising;

                fall_constraint(Setup_3_3) {

                     index_1 ("0.000932129,0.0331496,0.146240");

                     index_2 ("0.000932129,0.0331496,0.146240");

                     values ("0.035190,0.035919,0.049386", \

                             "0.047993,0.048403,0.061538", \

                             "0.082503,0.082207,0.094815");

                }

1.2 Hold Time

• data should be stable after the clock edge
• hold time is the amount of time the synchronous input (D) stays long enough after the capturing edge of clock so that the data can be stored successfully in the storage device.
• hold violation can be fixed by increasing the delay of the data path or by decreasing the clock uncertainty (skew) if specified in the design.

Hold Information .lib:

timing () {

              related_pin      : "CK";

              timing_type      : hold_rising;

              fall_constraint(Hold_3_3) {

                   index_1 ("0.000932129,0.0331496,0.146240");

                   index_2 ("0.000932129,0.0331496,0.146240");

                   values ("-0.013960,-0.014316,-0.023648", \

                           "-0.016951,-0.015219,-0.034272", \

                           "0.108006,0.110026,0.090834");

              }

Interconnect Delay --> Net delay + Cell Delay

In a digital design, a wire connecting pins of standard cells and blocks is referred to as a NET. A Net

- has only one driver
- has number of fanout cells or blocks
- can travel on multiple of metal layers of the chip.

"Net Delay" refers to the total time needed to charge to discharge all of the parasitic ( Capacitance / Resistance / Inductance)  of a given net. So we can say that net delay is a function of
- Net Resistance
- Net Capacitance
- Net Topology

Now to calculate the NET delay, the wires are modeled in different ways and there are different way to do the calculation. Practically, when you are applying a particular delay model in a design, then you have to apply that to all cells in a particular library.  You cannot mix delay models within a single library. There are a few recommendations provided by experts or experienced designer regarding the application of a Particular Delay model in a design and that depends on,
- technology of the design
- At what stage you are, and or say at what stage you want to apply a delay model
- how accurately you want to calculate the model

Note:
Ideally Till the physical wire is not  present in your design, you cannot calculate the net delay. Reason is .. if wire is not present,  you have no idea about width/length of the wires. So you can not calculate the accurate values of parasitic or say delay value of the wire. But here main point is accurate value , means there is possibility of inaccurate or say approximate value of delay value before physical laying of wire in a design.

There are several delay models. Those which can provide more accurate result, takes more run time to do the calculation, and those which are fast provides less accurate value of delay. Here are  a few of them, most popular delay models,

- Lumped Capacitor Model
- Lumped RC Model
- Distributed RC Model
     -pi RC Network
     -T RC Network
- RLC Model
- Wire Load Model
- Elmore Delay Model
- Transmission Line Model

STA: Delay -- Timing Path Delay

Questions:
I have a doubt regarding how delay is calculated alone a path . I think there are two ways
1)to calculate max delay and min delay, we keep adding max delays and min delays of all cells (buffer/inverter/max)from start point to end point respectively.
2)In other way, we calculate path delay for rising edge and falling edge separately. We apply a  rise edge at start point and keep adding cell delay. cell delay depends upon input transition and output fanout.  so now we have two path delay values for rise edge and falling edge. greater one is considered as Max delay and smaller one is min delay.
Which one is correct?

Short Ans is ... both are correct and you have to use both.  So here are a few details.

As we have mention that for setup and hold calculation, you have to calculate the delay of the timing path ( capture path or launch path). Now in a circuit there are 2 major type of Delay.
     1. CELL DELAY
         -- Timing delay between an input pin and an output pin of a cell.
         -- cell delay information is contained in the library of the cell. e.g- lef file
     2.  NET DELAY
          -- interconnect delay between a driver pin and a load pin.
          -- To calculate the NET delay generally you require 3 most important information.
                     - Characteristics of the Driver Cell ( which is driving the particular net)
                     - Load characteristic of the receiver cell . ( which is driven by the net)
                     - RC (resistance capacitance ) value of the net. ( it depends on several factor - which we                        will discuss later)

Both the delay can be calculated by multiple ways. It depends at what stage you require this information with in the design, e.g During pre layout or post layout or during Signoff timing. As per the stage you are using this, you can use different ways to calculate these delay. Sometime you require accurate numbers and sometime approximate numbers are also sufficient.

Now let's discuss this with previous background and then we will discuss few new concepts:

Now in the above fig, the delay of the circuit will be after calculating,
Delay = 0.5+0.04+0.62+0.21+0.83+0.15+1.01+0.12+0.57=4.05ns ( if all the delay in ns)

Now let's add few more values in this. As we know that every gate and net has max and min value, so in that case we can find out the max delay and min delay. ( on what basis these max delay or min delay we are calculating ... we will discuss after that).

so in the above example, first value is max value and 2nd value is min value. So
Delay(max) =0.5+0.04+0.62+0.21+0.83+0.15+1.01+0.12+0.57=4.05ns
Delay(min)=0.4+0.03+0.6+0.18+0.8+0.1+0.8+0.1+0.5=3.51ns

Now let's see what is the meaning of min and max delay.

The delay of a cell or net depends on various parameters. Few of them are listed below:

• library setup time
• library delay model
• external delay
• cell load characteristic
• cell drive characteristic
• operating condition (PVT)
• wire load model
• effective cell output load
• input skew
• back annotated delay

If any of these parameter vary, the delay very accordingly. Few of them are manually exclusive. and in what case we have to consider the effect of only one parameter at a time. If that's the case, then for STA, we calculated the delay in both the condition and then categorize them in worst (max delay) condition or the best condition (min delay). E.g - if a cell has different delay for rise edge and fall edge. Then we are sure that in delay calculation we have to use only one value. So as per their value, we can categorize fall and rise of all the cell in the max and min bucket. Ans finally we come up with max delay and min delay.

The way the delay is calculated also depends which tool are you using for STA or delay calculation. Cadence may have different algorithm from Synopsys and same is the case of other vendor tools like Mentor , and all. But in general the basic or say concepts always remain same.
Here is an example about the circuit, and you want to calculate the delay.

In the above diagram, we have 2 paths between UFF1 and UFF3. So whenever we are doing setup and hold analysis, these path will be the part of launch path (arrival time), so lets assume we want to calculate the max and min value of delay between UFF1 and UFF3.

Informations1:

Basic Static Timing Analysis : "Setup and Hold Time"

What is Setup and Hold Time?

To understand the origin of the Setup and Hold time concepts first understand it with respect to a system as shown in the fig. An input DIN and external clock CLK are buffered and passed through combinational logic before they reach a synchronous input and a clock input of a D flipflop (positive edge triggered). Now to capture the data correctly at D flip flop, data should be present at the time of positive edge of clock signal at the C pin .
Note: Here we are assuming D flip flop is ideal so Zero hold and setup time for this.

There maybe only 2 condition.
Tpd DIN > Tpd Clk
- For capture the data at the same time when Clock signal (positive clock edge) reaches at pin C, you
   have to apply the input Data at pin DIN "Ts(in) = (Tpd DIN - Tpd Clk)" time before the positive
   clock edge at pin CLK.
- in other word, at DIN pin, data should stable "Ts(in)" time before the positive clock edge at CLK       pin.
- This time "T(s)in" is know as the setup time of the system.

Tpd DIN < Tpd Clk
 - For capture the data at the same time when clock signal (positive clock edge ) reaches at pin C,           input data at pin DIN should no change before "Th(in) = Tpd Clk - Tpd DIN" time.  If it will
    change, positive clock edge at Pin C will capture the next data.
-  in other word, at DIN pin, Data should be stable "Th(in)" time after the positive clock edge at CLK    pin.
- This time "Th(in)" is know as Hold Time of the System.

For the above condition it looks that both the condition can't exist at the same time and you are right.
But we have to consider a few more things in this.
- Worst case and best case (max delay and min delay)
   - because of environment condition or because of PVT, we can do this analysis for the worst case (max delay) and best case (min delay) also.
- shortest path or longest path (min delay and max delay)
   -  if combinational logic has multiple paths, we have to do this analysis for the shortest path (min delay) and longest path (max delay) also.

So we can say that above condition can be like this.
- Tpd DIN (max) > Tpd Clk (min)
     - setup time == Tpd DIN (max) - Tpd Clk (min)
- Tpd DIN (min) < Tpd Clk (max)
      - hold time  ==  Tpd Clk (max) - Tpd DIN (min)

for example for combinational logic delays are:
data path (max, min) = (5ns, 4ns)
clock path (max, min) = (4.5ns, 4.1ns)
then setup time = 5 - 4.1 = 0.9ns
hold time = 4.5 - 4 = 0.5ns

Now similar type of explanation we can give for a D flip-flop.  There is a combinational logic between C and Q, between D and Q of the flipflop. There are different delays in those combinational logic and based on there max and min value, a flipflop has setup and hold time. One circuitry of the positive edge triggered D flip is shown below.

 
 There are different ways for making the D flip-flop. Like by JK flip-flop, master slave flipflop, Using 2 D type latches etc. Since the internal circuitry is different for each type of flipflop, setup and hold time is different for every flip-flop.

Definition:
Setup Time:
- setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. This applied to synchronous circuits such as flipflop.
- or in short I can say that amount of time the Synchronous input (D) must be stable before the active edge of the clock.
- The time when the input data is available and stable before the clock pulse is applied is called setup time.

Hold Time:
- Hold time is the minimum amount of time the data signal  should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous circuits such as the flipflop.
- or in short I can say that amount of time the synchronous input (D) must be stable after active edge of the clock.
- the time after clock pulse where data input is held stable is called hold time.

setup and hold violation:
in simple language-
if setup time is Ts for a flip-flop and if data is not stable before the Ts time from active edge of the clock,  there is a setup violation at that flipflop. So if data is changing in the non-shaded area ( in the above figure) before active clock edge, then it's a setup violation.
And if hold time is Th for a flipflop and if data is not stable after Th time from active edge of the clock, there is a hold violation at that flipflop. So if data is changing in the non-shaded area ( in the above figure) after active clock edge, then it's a hold violation.

Static Timing Analysis: Timing Paths

Static Timing Analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations under worst-case conditions. It considers the worst possible delay through each logic element, but not the logical operation of the circuit.

In comparison to circuit simulation, static timing analysis is
.  faster -- It is faster because it does not need to simulate multiple test vectors.
.  more thorough -- It is more thorough because it checks the worst-case timing for all possible logic conditions, not just those sensitized by a particular set of test vectors.

Once Again Note Those Thing: Static Timing Analysis checks the design only for proper timing, not for correct logical functionality.

Static Timing Analysis seeks to answer the question, "Will the correct data be present at the data input of each synchronous device when the clock edge arrives, under all possible conditions?"

In static timing analysis, the word static alludes to the fact that this timing analysis is carried out in an input independent manner. It locates the worst-case delay of the circuit over all possible input combinations. There are huge of numbers of logic paths inside a chip of complex design. The advantage of STA is that it performs timing analysis on all possible paths ( whether they are real or potential false paths)
However, it is worth noting that STA is not suitable for all design styles. It has proven efficient only for fully synchronous designs. Since the majority of chip design is synchronous, it has become a mainstay of chip design over the last few decades.

The Way STA is performed on a given circuit:
To check a design for violations or say to perform STA there are there are 3 main steps:
. Design is broken down into sets of timing paths.
. Calculates the signal propagation delay along each path.
. And checks for violations of timing constraints inside the design and at the input/output interface.

The STA tool analyzes ALL paths from each and every startpoint to each and every endpoint and compares it against the constraint that (should) exist for that path. All path should be constrained, most paths are constrained , most paths are constrained by the definition of the period of the clock, and the timing characteristics of the primary inputs and outputs of the circuit.

Before we start this we should know a few key concepts in STA method:
timing path, arrive time, required time, slack and critical path.
Let's talk about these one by one in detail.

Timing Paths:
Timing Paths can be divided by as per the type of signals ( e.g. clock signal, data signal, etc)

Type of Paths for timing analysis :
- Data Path
- Clock Path
- Clock Gating Path
- Asynchronous Path

Each Timing Path has a "start point" and an "end point".  Definition of Start Point and End Point vary as per the type of the timing path-. The Start Point is a place in the design where data is launched by a clock edge. The data is propagated through combinational logic in the path and then captured at the endpoint by another clock edge.

Startpoint and Endpoint are different for each type of paths. It's very important to understand this clearly to understand and analysing the Timing Analysis Report and Fixing the timing violation.

- Data Path
    - Start Point
       Input Port of the Design ( because the input data can be launched from some external source).
       Clock Pin of the flip-flop/latch/memory ( sequential cell)
    - End Point
        Data Input Pin of the flip-flop/latch/sequential cell)
        Output Port of the design (because the output data can be captured by some external sink).

- Clock Path
     - Start Point
        Input Port of the design
     -  End Point
        Set/Reset/Clear Pin of the flip-flop /latch/sequential cell

Data Paths:

If we use all the combinational of 2 types of Starting Point and 2 types of End Point, we can say that there are that there are 4 types of timing paths on the basis of Start Point and End Point.
 - Input Pin/Port to Register (flip-flop).
 - Input Pin/port to Output Pin/Port
 - Register (flip-flop) to Register (flip-flop)
 - Register (flip-flop) to output pin/port.

Please see the following fig:

PATH1 - starts at an input port and ends at the data input of a sequential element.(input port to           register)
PATH2 - starts at the clock pin of a sequential element and ends at the data input of a sequential element. ( register to register )
PATH3 - starts at the clock pin of a sequential element and ends at an output port. (Register to output port)
PATH4 - starts at an input port and ends at an output port. ( Input port to output port).

Clock Path:
Please check the following fig:

In the above fig its very clear that for the clock path the starts from the input port/pin of the design which is specific for the Clock input and the end point is the clock pin of sequential element. In between the Start point and the end point there may be lots of buffers/inverters/clock divider.

setup and hold time violations

Few important things to note down here -
-- Data is launched from FF1/D to FF1/Q at the positive clock edge at FF1/C.
-- At FF2/D,  input data is coming from FF1/Q through a conbinational logic.
-- Data is capturing at FF/D, at the positive clock edge at FF2/C
-- So I can say that launching flip-flop is FF1 and capturing flip-flop is FF2.
-- So data path is FF1/C --> FF1/Q --> FF2/D
-- For a single cycle circuit, Signal has to be propagate through data path in one clock cycle. Means if    data is launched at time = 0ns from FF1 then it should be captured at time = 10 ns  by FF2.
So for setup analysis at FF2, data should be stable "Ts" time before the positive edge at FF2/C. Where     "Ts" time is the setup time of FF2.
-- If  Ts = 0ns, then, data launched from FF1 at time = 0ns should arrive at D of FF2 before or at time
   = 10ns. If data takes too long ( greater than 10ns) to arrive ( means it is not stable before clock edge
   at FF2), it is reported as setup violation.
    If Ts = 1 ns, then, data launched from FF1 at time = 0ns should arrive at D of FF2 before or at            time = (10ns - 1ns) = 9ns . If data takes too long (greater than 9ns) to arrive ( means it is not stable
   before 1 ns of clock edge at FF2), it is reported as setup violation.

For hold analysis at FF2, data should be stable "Th" time after the positive edge at FF2/C, where "Th" is the hold time of FF2. Means there should not be any change in the input data at FF2/D between positive edge of clock at FF2 at Time = 10ns and Time = 10ns + Th.
-- To satisfy the hold condition at FF2 for the data launched at FF1 at 0ns, the data launched by FF1 at 10ns should not reach at FF2/D before 10ns + Th.
-- If Th = 0.5 ns, then we can say that the data launched from FF1 at time 10ns does not get propagated so soon that it reaches at FF2 before time (10+0.5) = 10.5ns ( or say it should reach from FF1 to FF2 with in 0.5ns ). If data arrive so soon ( means with in 0.5ns from FF1 to FF2, data can't be stable at FF2 for time = 0.5ns after the clock edge at FF2), its reported Hold violation.

With above explanation, there is 2 important things;
1. Setup is checked at next clock edge.
2. Hold is checked at same clock edge.

Setup check timing can be more clear for the above flip-flop combination with the help of following explanation.

In the above fig you can see that data launched at FF1/D ( at launch edge) reaches at FF2/D after a specific delay ( CLK-to-Q delay + Combinational Logic Delay) well before the setup time requirement of Flip-Flop FF2, so there is no setup violation.
From the fig its clear that if Slack = Required Time - Arrival Time < 0 (-ive) , then there is a setup violation at FF2.

Hold Check Timing can be more clear with the help of following circuit and explanation.

In the above fig you can see that there is a delay in the CLK and CLKB because of delay introduced by the serious of buffer  in the clock path. Now flip-flop FF2 has a hold requirement and as per that data should be constant after the capture edge of CLKB at Flip-Flop FF2.
You can see that desired data which suppose to capture by CLKB at FF2.D should be at Zero (0) logic state and be constant long enough after the CLKB capture edge to meet hold requirement but because of very short of logic delay between FF1/Q and FF1/D, the change in the FF1/Q propagates very soon. As a result of that there occurs a Hold violations.
This type of violation (hold violation)can be fixed by shorting the delay in the clock line or by increasing the delay in the data path.

Setup and Hold violation calculation for the single clock cycle path is very easy to understand. But the complexity increases in case of multi-cycle path, Gated clock, flip-flop using different clocks, latches in place of Flip-Flop.

Specifying the Maximum Transition Constraint

Maximum transition constraints can come from a user input, library, and library pin. User-specified maximum transition constraints are expressed with the main library derate and slew threshold of PrimeTime.  The set_max_transition command sets a maximum limit on the transition time for all specified pins, ports, designs, or clocks. When specified on clocks, pins in the clock domain are constrained. Within a clock domain, you can optionally restrict the constraint further to only clock paths or data paths, and to only rising or falling transitions. During constraint checking on a pin or port, the most restrictive constraint specified on a design, pin, port, clock ( if the pin or port is in that clock domain), or library is considered. This is also true where multiple clocks launch the same path.
The set_max_transition command places the max_transition attribute, which is a design rule constraint, on a specified objects. In Prime Time, the slews and maximum transition constraint attributes are reported in the local threshold and derate of each pin or library.

To view the maximum transition constraint evaluations, use the report_constraint -max_transition cmd.  Prime Time reports all constraints and slews in the threshold and derate of the pin of the cell instance, and the violations are sorted on the absolute values ( that is, they are expressed in that of design threshold and derate ). You can also use the report_constraint command to report constraint calculations only for maimum capacitance and maximum transition for a specified port or pin list. Use the object_list option to specify a list of pins or ports in the current design that you want to display constraint related information.

To see the port maximum transition limit, sue the report_port -design_rule command. To see the default maximum transition setting for the current design, sue the report_design command. To undo maximum transition limits previously set on ports , pins, designs, or clocks, use remove_max_transition.

setting a maximum transition limit.
To set a maximum transition limit of 2.0 units on the ports of OUT*, enter
pt_shell> set_max_transition 2.0 [get_ports "OUT*"]

To set the default maximum transition limit of 5.0 units on the current design, enter
pt_shell> set_max_transition 5.0 [current_design]

To set the maximum transition limit of 4.0 on all pins in the CLK1 clock domain , for rising transitions in data paths only, enter
pt_shell> set_max_transition 4.0 [get_clocks CLK1] -data_path -rise

specifying the timing derating factors

Timing derating factors model the effects of varying operating conditions by adjusting the delay values calculated for the individual timing arcs of a block. By default, the timing derating factors are 1.0 and the tool does not adjust the calculated delay values.
To set derating factors, use the set_timing_derate cmd and specify the following information:
-- the derating factor
-- whether the derating factor is for early or late delays by using the -early or -late options.
Optionally , you can apply the derating factor to
-- Specific leaf-level instance, hierarchical instance, or library cell by specifying the object.
    By default, it applies to the current block.
--Rise or fall delays only by using the -rise or -fall options.
    by default, it applies to both rise and fall delays.
-- clock or data paths only by using the -clock or -data options
    by default, it applies to both clock and data path.
-- net delays, cell delays, or cell timing checks by using the -net_delay, -cell_delay, or cell_check option. by default, it applies to all three.
-- A specific cornet by using the -corners option.
By default , it applies to the current corner.
The following example reduces all minimum delay by 10 percent and increase all maximum delays by 20 percent for the current cornet:
icc_shell> set_timing_derate -early 0.9 -late 1.2

To report the derating factors, use the report_timing_derate cmd. By default, the cmd reports the derating factors for all corners. To report the derating factors for specific corners, use the -cornet option.

To reset the derating factors to 1.0, use the reset_timing_derate cmd. By default, the cmd resets the derating factors for the current corner for the current block and all its instances. To reset the derating factors for specific corners, use the -corners option. To reset the derating factors for specific objects, specify the objects.

How can I selectively reset the global timing derate values?

Questions:
I have set the following global timing derate values:
pt_shell>set_timing_derate -late 1.05
pt_shell>set_timing_derate -early 0.95
Now, I want to reset the timing derate values on a specific instance, for example, U1;
pt_shell> reset_timing_derate [get_cells U1]
why is this command not resetting the timing derate values on the instance?

Answer:
The following cmds set the timing derate values globally on the entire current design:
pt_shell>set_timing_derate -late 1.05
pt_shell>set_timing_derate -early 0.95
pt_shell> report_timing_derate

                                             ----------Clock-----------                            -----------Data-----------------
                                        Rise                        Fall                      Rise                                  Fall
                                 Early        Late        Early      Late        Early    Late                 Early          Late
---------------------------------------------------------------------------------------------------------------------------------------------------
Design: test
Net delay static          0.95        1.05         0.95      1.05        0.95    1.05                  0.95           1.05
Net delay dynamic     0.95        1.05         0.95      1.05        0.95    1.05                  0.95           1.05
Cell Delay                  0.95        1.05         0.95      1.05        0.95    1.05                  0.95           1.05
Cell Check                    ---          ---            ---          ---            ---       ---                      ---              ---

Resetting derate values on instance U1 of the design only resets the timing derate values specifically set earlier on instance U1 but does not override the global timing derate settings:
pt_shell> set_timing_derate 1.55 -cell_delay -late [get_cells U1]
pt_shell> set_timing_derate 0.55
pt_shell> report_timing_derate [get_cells U1]

                                          ---------clock------------                    ------------Data------------

                                       Rise                    Fall                     Rise                       Fall

                                 Early      Late         Early   Late        Early   Late           Early    Late

-------------------------------------------------------------------------------------------------------------------------------

Cell(leaf):U1               0.55       1.55          0.55   1.55        0.55   1.55             0.55     1.55

Cell delay

2. Reset all timing derate values set globally on the complete current design:

pt_shell> reset_timing_derate

pt_shell>report_timing_derate [get_cells U1]

                            -------clock--------                            --------Data-------

                                      Rise                   Fall                       Rise                   Fall

                                Early     Late       Early    Late          Early    Late       Early    Late

---------------------------------------------------------------------------------------------------------------------

Cell(leaf):U1               ---        ---            ---        ---            ---          ---          ---        ---

    Cell delay

In conclusion, the reset_timing_derate cmd only resets the timing derate values at or below the scope where they were set. The cmd does not override the timing derate values set at a higher scope.

Constraints for PVT Corners

Normally Best/Worst PVT means the Fastest/Slowest operating condition of the circuit: typical Best(fastest) PVT is {process: fast, voltage: low, temperature: low} while worst  (slowest) PVT is {process: slow, voltage: high, temperature: high }.

However, recent technology process encounters inverse temperature effect, where cells might function faster at certain high temperature than low temperature, Thus it is suggested that you consult with the cell library provider on what PVT is fastest & slowest.


Notes:
The process fast means, that all transistors on the chip have combination of parameters which gives the minimum cell delay.

Also, We should know about RC corners. The width and thickness of wires (metal) are also may vary from chip to chip ( even on one chip:).  So , for the setup check, we should use RCWorst corner for extraction and one of PVT corners that gives you the max cell delay.

Explanation of Deration and OCV

1) Derating is simply another way of adding margin to the design. This allows you to scale all delays by a certain percentage to increase margin. This is not an SDC constraint, but a variable to set within the tool run script.

2) OCV is a timing mode ( like a single or BC/WC). This allows you to use variation from the libraries in performing timing checks for ensuring worst case scenarios.

How to fix max transition time violations?

The max transition time is one of the three Design Rules ( max fanout, max transition, max capacitance).

It is much more important than setup/hold timing.
As we all know, in STA, the delay of each std. cells is calculated from looking up the NLDM ( non-linear delay model) tables which is defined in library. These tables are two factors: input transition time, and output load. The result of table is the delay value of cell under certain transition and output load.

If the input transition or output load is out of range is within but not the values in NDLM, interpolation is utilized to calculate.
If the input transition or output load is out of range of NLDM , ext-interpolation is used to calculation. But it is natural the result would be rather in-accurate.

So the STA will be rather in-accurate. Timing analysis is un-believable.
Now, you can understand how important max tran is.
-- one more reason of fixing max transition violation is that bigger transition will result in bigger DC
    power consumption.
-- The margin in 30% of max transition is allowed.
For example, if the constraint of max transition is 1 ns, then 1.3 ns is allowed.

PVT Corners

Generally in most user environments, the process, voltage, and the temperature (PVT) point is specified by referring to a predefined operating condition in  a specific timing library. The library operating condition provides the system with values for P, V, and T, and these then are used to calculate derating parameters and other aspects of the analysis.

However, these are situations when there are no predefined operating conditions in the user timing libraries or the pre-existing operating conditions are not consistent with the user's operating environment.

On-Chip Variation Delay Analysis

During timing analysis, the tool uses the on-chip variation(OCV) mode to perform timing, which models the effects of variation in operating conditions across the chip. This mode performs a conservative timing analysis by simultaneously applying minimum and maximum delays to different paths.

For a setup check, the tool uses maximum delays for the launch clock path and data path and minimum delays for the capture clock path, as shown in the following figure.

slack

The amount of time by which a violation is avoided is called the slack.

For example,
for a setup constarint, it a signal must reach a cell input at no later than 8ns and is determined to arrive at 5 ns, the slack is 3 ns. A slack of 0 means that the constraint is just barely satisfied. A negative slack indicates a timing violation.

constraint checking

After PT determines the timing paths and calculates the path delays, it can check for violations of timing constraints, such as setup and hold constraints.

A setup constraint specifies how much time is necessary for data to be available at the input of a sequential device before the clock edge that captures the data in the device. This constraint enfores a maximum  delay on the data path relative to the clock path.

A hold constraint specifies how much time is necessary for data to be stable at the input of a squential device after the clock edge that captures the data in the device. This constraint enfores a minimum delay on the data path relative to the clock path.

In addition to setup and hold constraints, PT can also check recovery/removal constraints, data-to-data constraints, clock-gating setup/hold constraints, and minimum pulse width for clock signals.

Timing Exceptions

When certain paths are not intended to operate according to the default setup/hold behavior assumed by PT,  you shoulf specify those paths as timing exceptions. Otherwise, PT might incorrectly report those paths as having timing violations.

PT lets you specify the following types of timing exceptions:

** false path --A path that is never sensitzed due to the logic configuration, expected data sequence, or operating mode.

** Multicycle Path -- A path designed to take more than one clock cycle from launch to capture.

** Minimum/maximum delay path -- A path that must meet a delay constraint that you specify explicity as a time value.

setup and hold checks

Notes,
Assume that the flip-flops are defined in the technology library to have a minimum setup time 1.0 time units and a minimum hold time of 0.0 time units. The clock period is defined in PT to be 10 time units. ( The time unit size, such as ns or ps, is specified in the technology library).

By Default, PT assumes that signals are to be propagated through each data path in one clock cycle. Therefore, when PT performs a setup check, it verifies that the data path delay is small enough so that data launched from FF1 reaches FF2 within one clock cycle, and arrives at least 1.0 time unit before the data gets captured by the next clock edge at FF2. If the data path delay is too long, it is reported as a timing violation. For this setup check, PT considers the longest possible delay along the data path and the shortest possible delay along the clock path between FF1 and Ff2.

When PT performs a hold check, it verifies that the data launched from FF1 reaches FF2 no sooner than the capture clock edge for the previous clock cycle. This check ensures that the data already existing at the input of FF2 remains stable long enough after the clock edge that captures data for the previous cycle. For this hold check, PT considers the shortest possible delay along the data path and the longest possible delay along the clock path between FF1 and FF2.  A hold violation can occur if the clock path has a long delay.