Timing Exceptions

When certain paths are not intended to operate according to the default setup/hold behavior assumed by PT,  you shoulf specify those paths as timing exceptions. Otherwise, PT might incorrectly report those paths as having timing violations.

PT lets you specify the following types of timing exceptions:

** false path --A path that is never sensitzed due to the logic configuration, expected data sequence, or operating mode.

** Multicycle Path -- A path designed to take more than one clock cycle from launch to capture.

** Minimum/maximum delay path -- A path that must meet a delay constraint that you specify explicity as a time value.

setup and hold checks

Notes,
Assume that the flip-flops are defined in the technology library to have a minimum setup time 1.0 time units and a minimum hold time of 0.0 time units. The clock period is defined in PT to be 10 time units. ( The time unit size, such as ns or ps, is specified in the technology library).

By Default, PT assumes that signals are to be propagated through each data path in one clock cycle. Therefore, when PT performs a setup check, it verifies that the data path delay is small enough so that data launched from FF1 reaches FF2 within one clock cycle, and arrives at least 1.0 time unit before the data gets captured by the next clock edge at FF2. If the data path delay is too long, it is reported as a timing violation. For this setup check, PT considers the longest possible delay along the data path and the shortest possible delay along the clock path between FF1 and Ff2.

When PT performs a hold check, it verifies that the data launched from FF1 reaches FF2 no sooner than the capture clock edge for the previous clock cycle. This check ensures that the data already existing at the input of FF2 remains stable long enough after the clock edge that captures data for the previous cycle. For this hold check, PT considers the shortest possible delay along the data path and the longest possible delay along the clock path between FF1 and FF2.  A hold violation can occur if the clock path has a long delay.

Cell Delay and Net Delay

Cell Delay

Cell Delay is the amount of delay from input to output of a logic gate in a path. PT calculates the cell delay from delay tables provided in the technology library for the cell.


Net Delay
Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path.
This delay is caused by the parasitic capacitance of the interconnection between the two cells, combined with net resistance and the limited drive strength of the cell driving the net.

Delay Calculation

The total delay of a path is the sum of all cell and net delays in the path.

The method od delay calculation depends on if chip layout has been completed.
Before layout, the chip topography is unknown, so PT must estimate the net delays using wire load models.

After layout, an external tool can accurately determine the delays and write them to a StandardDelay Format(SDF)file. PT can read the SDF file and back-annotate the design with the delay information for layout-accurate timing analysis. PT can also accept a detailed description of parasitic capacitors and resistors in the interconnection network, and then accurately calculate net delays based on that information.

Path Types

Path Types:

--Clock path ( a path from a clock input port or cell pin, through one or moew buffers or inverters, to the  clock pin or a sequential element) for data setup and hold checks.

--Clock-gating path ( a path from an input port to a clock-gating element) for clock-gating setup and hold checks

--Asynchronous path ( a path from an input port to an asynchronous set or clear pin of a sequential element) for recovery and removal checks.

timing paths

timing paths

In this figure, Each path starts at a data point, passes through some combinational logic, and ends at a data capture point:

* path 1 starts at an input port and ends at the data input of a sequential element.
* path 2 starts at the clock pin of a sequential element and ends at the data input of a sequential element.
* path 3 starts at the clock pin of  a sequential element and ends at an output port.
* path 4 starts at an input port and ends at an output port.

Notes:
Each path has a startpoint and an endpoint. The startpoint is a place in the design where data is launched by a clock edge. The data is propagated through combinational logic in the path and then captured at the end point by another clock edge.
The startpoint of a path is a clock pin of a sequential element, or possibly an input port of the design ( because the input data can be launched from some external source.) The endpoint of a path is a data input pin of a sequential element, or possibly an output port of the design ( because the output data can be captured by some external sink).

STA

It is said as static because the timing information is obtain through calculation, not by simulation.

STA analysis the delay of all paths register to register, input to register, register to output and check if there is a violation.

If the delay of one path is too large, there will be setup violation.  The target register will sample the old value.

If the delay of one path is too small, there will be hold tie violation. The target register will sample the next value.

Both of two situation will cause error.