Cell Delay and Net Delay

Cell Delay

Cell Delay is the amount of delay from input to output of a logic gate in a path. PT calculates the cell delay from delay tables provided in the technology library for the cell.


Net Delay
Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path.
This delay is caused by the parasitic capacitance of the interconnection between the two cells, combined with net resistance and the limited drive strength of the cell driving the net.