Delay Calculation

The total delay of a path is the sum of all cell and net delays in the path.

The method od delay calculation depends on if chip layout has been completed.
Before layout, the chip topography is unknown, so PT must estimate the net delays using wire load models.

After layout, an external tool can accurately determine the delays and write them to a StandardDelay Format(SDF)file. PT can read the SDF file and back-annotate the design with the delay information for layout-accurate timing analysis. PT can also accept a detailed description of parasitic capacitors and resistors in the interconnection network, and then accurately calculate net delays based on that information.