setup and hold checks

Notes,
Assume that the flip-flops are defined in the technology library to have a minimum setup time 1.0 time units and a minimum hold time of 0.0 time units. The clock period is defined in PT to be 10 time units. ( The time unit size, such as ns or ps, is specified in the technology library).

By Default, PT assumes that signals are to be propagated through each data path in one clock cycle. Therefore, when PT performs a setup check, it verifies that the data path delay is small enough so that data launched from FF1 reaches FF2 within one clock cycle, and arrives at least 1.0 time unit before the data gets captured by the next clock edge at FF2. If the data path delay is too long, it is reported as a timing violation. For this setup check, PT considers the longest possible delay along the data path and the shortest possible delay along the clock path between FF1 and Ff2.

When PT performs a hold check, it verifies that the data launched from FF1 reaches FF2 no sooner than the capture clock edge for the previous clock cycle. This check ensures that the data already existing at the input of FF2 remains stable long enough after the clock edge that captures data for the previous cycle. For this hold check, PT considers the shortest possible delay along the data path and the longest possible delay along the clock path between FF1 and FF2.  A hold violation can occur if the clock path has a long delay.