Implementing the Clock Trees

The recommended process for implementing the clock trees in the design is to use the clock_opt command, which performs clock tree synthesis and incremental physical optimization. This process results in a timing optimization design with fully implemented clock trees.

Note:
Before implementing the clock trees, save the design. This allows you to refine the clock  tree synthesis goals and rerun clock tree synthesis with the same starting point, if necessary.

By default, ICC uses the following naming convention for buffers and inverters inserted during clock tree synthesis

reference_GxByIz

Where reference is the library reference cell of the buffer or inverter, x is the gate level, y is the buffer level, and z is the instance count.  To more easily locate the inserted buffers and inverters in your netlist, you can add a prefix to the instance names by setting the cts_instance_name_prefix variable. Similarly , you can add a prefix to any nets inserted during clock tree synthesis by setting the cts_net_name_prefix variable.

To perform clock tree synthesis, clock tree optimization, and incremental physical optimization, use the clock_opt command or choose Clock > Core CTS and Optimization in the GUI.

By default, ICC ignores the dont_touch attribute on cells and nets during clock tree synthesis and clock tree optimization.  To prevent sizing of cells during clock tree synthesis and clock tree optimization, use the set_clock_tree_exceptions -dont_size_cells command.

By default, the clock_opt command uses virtual routing during clock tree synthesis, but the optimization process uses the integrated clock global router to estimate the wire delay and capacitance. To ensure better postroute correlation, the integrated clock global router saves clock global routing information in the Milkyway database to be used by clock routing.

The clock_opt command does the following:
1. (Optional) Performs clock tree power optimization
    To perform clock tree power optimization during the clock_opt process, enable physical optimization of the integrated clock-gating cells and power-aware placement, use the -power option of the clock_opt command.

2. Synthesizes the clock trees
Before implementing the clock tress, ICC upsizes, and possible moves, the existing clock gates, which can improve the quality of results (QoR) and reduce the number of clock tree levels.
Note:
To prevent the upsizing of existing clock gates before clustering, set the cts_prects_upsize_gates variable to false. To prevent the moving of existing clock gates before clustering, set the cts_move_clock_gate variable to false.

In addition, ICC might move the existing gates, including integrated clcok-gating (ICG) cells, when this could improved QoR. To prevent ICC from moving existing gates, including integrated clock-gating cells, before clustering, set the cts_move_clock_gate variable to false.

ICC builds clock trees that meet the clock tree design rule constraints, while balancing the loads and minimizing the clock skew. In addtion, ICC optimizes the clock paths beyond exlcude pins, stop pins, and float pins to fix any design rule constraint violations.

Note:
Optimization is not performed on don't buffer nets or inside interface logic models (ILMs).

By default, the clock sink cells might be moved or sized during the legalization and optimization steps that occur after clock tree synthesis. To prevent any modification to the clock sink cells after clock tree synthesis, set the cts_fix_clock_tree_sinks variable to true. Note that fixing the clock sinks can impact the timing QoR.

You can also run clock tree synthesis as a standalone process, using the compile_clock_tree command.

3. Optimizes the clock trees
During clock tree optimization, ICC uses the optimization techniques, such as buffer relocation, buffer sizing, delay insertion, gate sizing, and gate relocation, to further improve the skew.

Note:
During clock tree optimization, ICC ignores the dont_touch attribute on cells and nets. To prevent sizing of cells during clock tree optimization, use the set_clock_tree_exceptions -dont_size_cells command.

You can also run clock tree optimization as a standalone process, using the optimize_clock_tree command.

4. (Optional) Performs interclock delay balancing
To perform interclock delay balancing during the clock_opt process, define the interclock delay balancing requirements, and use the -inter_clock_balance option of the clock_opt command.

Note:
   ICC performs interclock delay balancing by performing delay insertion at the clock root. If the clock root net has a don't buffer net exception, ICC cannot perform interclock delay balancing.
   If the clock root is defined as a port of a pad cell, the delay insertion is peformed on the net driven by the pad cell.

You can also run interclock delay balancing as a standalone process, using the balance_inter_clock_delay command.

5. Performs detail routing of the clock nets
You can also perform detail routing of the clock nets as a standalone process, using the route_zrt_group -all_clock_nets -reuse_existing_global_route true command.
To prevent routing of the clock nets, use the -no_clock_route option of the clock_opt command.

6. Performs RC extraction of the clock nets and computes accurate clock arrival times .

7. (Optional) Adjusts the I/O timing
To adjust the input and output delay based on the actual clock arrival times, use the
-update_clock_latency option of the clock_opt command. ICC uses the adjusted input and output delays during placement and timing optimization.

You can also update the I/O timing as a standalone process, using the update_clock_latency command.

8. (Optional) Optimizes the scan chains
To optimize the scan chains by reordering the chains to minimize the number of buffer crossings in the scan chain, use the -optimize_dft option of the clock_opt command.

9. Fixes the placement of the clock tree buffers and inverters.

10. Performs placement and timing optimization.
If you specify -update_clock_latency, ICC uses the adjusted input and output delays during placement and timing optimization. ICC uses propagated arrival times for all clock sinks.

You can customize the placement and timing optimization process by specifying the following options: -area_recovery, -in_place_size_only, and -size_only.  You can perform leakage optimization and -power.
You can also run only placement and timing optimization as a standalone process, using the psynopt command.
To prevent placement and timing optimization, use the -only_cts option of the clock_opt command.

To run only placement and timing optimization ( and not clock tree synthesis, clock tree optimization, or clock tree routing), use the -only_psyn option of the clock_opt command.

11. (Optional) Performs power optimization
You can perform leakage power optimization and dynamic power optimization during the clock_opt process by enabling the selected optimizations with the set_power_options command and using the -power option of the clock_opt command. To enable leakage power optimization, use the set_power_options -leakage command. To enable dynamic power optimization, use the set_power_options -dynamic command.

12. (Optional) Fixes hold time violations
To fix hold time violations during the clock_opt process, use the -fix_hold_all_clocks option of the clock_opt command.