Interconnect Delay --> Net delay + Cell Delay

In a digital design, a wire connecting pins of standard cells and blocks is referred to as a NET. A Net

- has only one driver
- has number of fanout cells or blocks
- can travel on multiple of metal layers of the chip.

"Net Delay" refers to the total time needed to charge to discharge all of the parasitic ( Capacitance / Resistance / Inductance)  of a given net. So we can say that net delay is a function of
- Net Resistance
- Net Capacitance
- Net Topology

Now to calculate the NET delay, the wires are modeled in different ways and there are different way to do the calculation. Practically, when you are applying a particular delay model in a design, then you have to apply that to all cells in a particular library.  You cannot mix delay models within a single library. There are a few recommendations provided by experts or experienced designer regarding the application of a Particular Delay model in a design and that depends on,
- technology of the design
- At what stage you are, and or say at what stage you want to apply a delay model
- how accurately you want to calculate the model

Note:
Ideally Till the physical wire is not  present in your design, you cannot calculate the net delay. Reason is .. if wire is not present,  you have no idea about width/length of the wires. So you can not calculate the accurate values of parasitic or say delay value of the wire. But here main point is accurate value , means there is possibility of inaccurate or say approximate value of delay value before physical laying of wire in a design.

There are several delay models. Those which can provide more accurate result, takes more run time to do the calculation, and those which are fast provides less accurate value of delay. Here are  a few of them, most popular delay models,

- Lumped Capacitor Model
- Lumped RC Model
- Distributed RC Model
     -pi RC Network
     -T RC Network
- RLC Model
- Wire Load Model
- Elmore Delay Model
- Transmission Line Model