STA: Delay -- Timing Path Delay

Questions:
I have a doubt regarding how delay is calculated alone a path . I think there are two ways
1)to calculate max delay and min delay, we keep adding max delays and min delays of all cells (buffer/inverter/max)from start point to end point respectively.
2)In other way, we calculate path delay for rising edge and falling edge separately. We apply a  rise edge at start point and keep adding cell delay. cell delay depends upon input transition and output fanout.  so now we have two path delay values for rise edge and falling edge. greater one is considered as Max delay and smaller one is min delay.
Which one is correct?

Short Ans is ... both are correct and you have to use both.  So here are a few details.

As we have mention that for setup and hold calculation, you have to calculate the delay of the timing path ( capture path or launch path). Now in a circuit there are 2 major type of Delay.
     1. CELL DELAY
         -- Timing delay between an input pin and an output pin of a cell.
         -- cell delay information is contained in the library of the cell. e.g- lef file
     2.  NET DELAY
          -- interconnect delay between a driver pin and a load pin.
          -- To calculate the NET delay generally you require 3 most important information.
                     - Characteristics of the Driver Cell ( which is driving the particular net)
                     - Load characteristic of the receiver cell . ( which is driven by the net)
                     - RC (resistance capacitance ) value of the net. ( it depends on several factor - which we                        will discuss later)

Both the delay can be calculated by multiple ways. It depends at what stage you require this information with in the design, e.g During pre layout or post layout or during Signoff timing. As per the stage you are using this, you can use different ways to calculate these delay. Sometime you require accurate numbers and sometime approximate numbers are also sufficient.

Now let's discuss this with previous background and then we will discuss few new concepts:

Now in the above fig, the delay of the circuit will be after calculating,
Delay = 0.5+0.04+0.62+0.21+0.83+0.15+1.01+0.12+0.57=4.05ns ( if all the delay in ns)

Now let's add few more values in this. As we know that every gate and net has max and min value, so in that case we can find out the max delay and min delay. ( on what basis these max delay or min delay we are calculating ... we will discuss after that).

so in the above example, first value is max value and 2nd value is min value. So
Delay(max) =0.5+0.04+0.62+0.21+0.83+0.15+1.01+0.12+0.57=4.05ns
Delay(min)=0.4+0.03+0.6+0.18+0.8+0.1+0.8+0.1+0.5=3.51ns

Now let's see what is the meaning of min and max delay.

The delay of a cell or net depends on various parameters. Few of them are listed below:

• library setup time
• library delay model
• external delay
• cell load characteristic
• cell drive characteristic
• operating condition (PVT)
• wire load model
• effective cell output load
• input skew
• back annotated delay

If any of these parameter vary, the delay very accordingly. Few of them are manually exclusive. and in what case we have to consider the effect of only one parameter at a time. If that's the case, then for STA, we calculated the delay in both the condition and then categorize them in worst (max delay) condition or the best condition (min delay). E.g - if a cell has different delay for rise edge and fall edge. Then we are sure that in delay calculation we have to use only one value. So as per their value, we can categorize fall and rise of all the cell in the max and min bucket. Ans finally we come up with max delay and min delay.

The way the delay is calculated also depends which tool are you using for STA or delay calculation. Cadence may have different algorithm from Synopsys and same is the case of other vendor tools like Mentor , and all. But in general the basic or say concepts always remain same.
Here is an example about the circuit, and you want to calculate the delay.

In the above diagram, we have 2 paths between UFF1 and UFF3. So whenever we are doing setup and hold analysis, these path will be the part of launch path (arrival time), so lets assume we want to calculate the max and min value of delay between UFF1 and UFF3.

Informations1:

                          NOR4       UNAND6    UNAND0    UBUF2     UOR2    
--------------------------------------------------------------------------------------------------------------------------
delays(ns)             5                   6                  6                  2             5
--------------------------------------------------------------------------------------------------------------------------

Calculation:
Delay in Path1:   5+6=11ns
Delay in Path2:   6+2+5+6=19ns
so
Max Delay = 19ns -- Path2 -- Longest Path -- Worst Path
Min Delay = 11ns -- path1 - smallest path -- best path


Information2:

                                 NOR4       UNAND6    UNAND0    UBUF2     UOR2    

--------------------------------------------------------------------------------------------------------------------------
Rise delay(ns)             5                   6                  4                1                1
--------------------------------------------------------------------------------------------------------------------------
Fall delay(ns)              6                    7                  3                1                 1
--------------------------------------------------------------------------------------------------------------------------

Calculation:
Delay in path1:   Rise Delay: 5+6=11ns          fall delay 6+7=13ns
delay in path2:    rise delay: 4+1+1+6=12ns    fall delay 3+1+1+7=12ns
so
max delay = 13ns -- path1 (fall delay)
min delay = 11ns -- path1 (rise delay)

information3:

                                                               NOR4       UNAND6    UNAND0    UBUF2     UOR2    

--------------------------------------------------------------------------------------------------------------------------
        Rise delay(ns)                                        5                 6                  4                1                1
Min ----------------------------------------------------------------------------------------------------------------
         Fall delay(ns)                                         6                 7                  3                1               1
-----------------------------------------------------------------------------------------------------------------------
         Rise delay(ns)                                       5.5               6.5               4.5            1.5             1.5
Max ----------------------------------------------------------------------------------------------------------------
         Fall delay(ns)                                         5.5              6.5                2.5           0.5             0.5
-----------------------------------------------------------------------------------------------------------------------

Calculation:
for min library:
delay in path1:  rise delay: 5+6=11ns              fall delay:  6+7=13ns
delay in path2:  rise dealy:  4+1+1+16=12ns   fall delay:  3+1+1+7=12ns
for max libary:
delay in path1:  rise delay: 5.5+6.5=12ns         fall delay: 5.5+6.5=14ns
delay in path2:  rise delay: 4.5+1.5+1.5+6.5=14ns   fall delay: 2.5+0.5+0.5+6.5=10ns
so
max delay = 14ns -- path1 (fall delay)/path2(rise delay)
min delay = 10ns -- path2

As we have calculated above, the STA tool also use similar approach for finding the max delay and min delay. Once max and min delay is calculated then during setup and hold calculation, we use corresponding value.