low power techniques

We can use the following techniques for a low power design.
1. power gating
2. multiple supply voltages (multi-VDD)
3. voltage scaling.
4.Multi-threshold CMOS (Multi-VT)
5.Adaptive Body-Biasin
6. clock gating

Power Gating: UPF (Unified Power Format)
Power gating is a technique used in integrated circuit design to reduce power consumption by shutting off to blocks of the circuit that are not in use. In addition to reducing stand-by or leakage power , power gating has the benefit of enabling Iddq testing.
The basic purpose of power gating is to temporarily shutting down blocks in a design when the blocks are not in use. This will reduce the leakage power of the chip. Power gating means switching off  an area of a design when its functionality is not require, and then restoring power when it is required. This temporary shutdown time can also called as "low power mode" or "inactive mode", again when we need that particular part of the design in operation then we can turn on the power and that state is called as "active mode".

Switching ON and OFF can be down either by software or hardware control. Th power supply of the entire design is cut off when the circuit is not in use. Such designs do not require data to be retained in the registers or latches used in the design. Functional verification of design is still required to make sure that the position of the designs that are awake function properly and also ensure that the system would work when power is restored in the sleeping part of the device.

When the power is shut off, each power domain must be isolated from rest of the design, so that it does not corrupt the downstream logic.  Power shutdown results in slow output from the power gated blocks. These output spends significant time at threshold voltage, causing large crowbar currents in the always on block, for this purpose we need isolation cells.

Isolation cells are used to prevent these crowbar currents. The isolation cells are placed between the output of the power gated blocks and inputs of the always on blocks.
Lets see the following 2 power domains D1 and D2. D1 is the power shut down domain and D2 is always-on. Now lets say there are a few signals from D1 to D2, suppose at any time if the D1 goes to in-active mode (Switched OFF) and if the signal traversing from D1 to D2 gets some noise or some unwanted signal from some source it can trigger the logic in the D2 domain, which will do unwanted functionality of the circuit, to prevent this Isolation cells are used in between the two domains.

Now if we have isolated the shut down domain from the other domain but we need to retain the last values stored in the registers in the shut down domain for this we use the retention Registers.
Retention Registers:
Retention cells are used in the low power domain to retain the values when the domain power goes into OFF state. these retention registers are special low leakage flip-flops used to hold the data of main register of the power gated block. Thus internal state of the block during power down mode can be retained and loaded back to it when the block is reactivated, retention registers are always powered up. The retention strategy is design dependent. During the power gating data can be retained and transferred back to block when power gating is withdrawn. Power gating controller controls the retention mechanism such as when to save the current contents of the power gating block and when to restore it back.

Level Shifters:
Level shifters are used in such a design where multi voltage supply have been used, now Consider the above two voltage domain D2 and D1 , if there are few signals from D2 (1.0 V) are travelling to D1 0.85V domain, their supply voltage is different then we need to insert level shifter in that domain.

The main function of level shifter is to shift the voltage of the particular domain as per the signal (from which domain it is coming).

Power Switches:
Power switches are used to switch off the power shut domain.