Basic Static Timing Analysis : "Setup and Hold Time"

What is Setup and Hold Time?

To understand the origin of the Setup and Hold time concepts first understand it with respect to a system as shown in the fig. An input DIN and external clock CLK are buffered and passed through combinational logic before they reach a synchronous input and a clock input of a D flipflop (positive edge triggered). Now to capture the data correctly at D flip flop, data should be present at the time of positive edge of clock signal at the C pin .
Note: Here we are assuming D flip flop is ideal so Zero hold and setup time for this.

There maybe only 2 condition.
Tpd DIN > Tpd Clk
- For capture the data at the same time when Clock signal (positive clock edge) reaches at pin C, you
   have to apply the input Data at pin DIN "Ts(in) = (Tpd DIN - Tpd Clk)" time before the positive
   clock edge at pin CLK.
- in other word, at DIN pin, data should stable "Ts(in)" time before the positive clock edge at CLK       pin.
- This time "T(s)in" is know as the setup time of the system.

Tpd DIN < Tpd Clk
 - For capture the data at the same time when clock signal (positive clock edge ) reaches at pin C,           input data at pin DIN should no change before "Th(in) = Tpd Clk - Tpd DIN" time.  If it will
    change, positive clock edge at Pin C will capture the next data.
-  in other word, at DIN pin, Data should be stable "Th(in)" time after the positive clock edge at CLK    pin.
- This time "Th(in)" is know as Hold Time of the System.

For the above condition it looks that both the condition can't exist at the same time and you are right.
But we have to consider a few more things in this.
- Worst case and best case (max delay and min delay)
   - because of environment condition or because of PVT, we can do this analysis for the worst case (max delay) and best case (min delay) also.
- shortest path or longest path (min delay and max delay)
   -  if combinational logic has multiple paths, we have to do this analysis for the shortest path (min delay) and longest path (max delay) also.

So we can say that above condition can be like this.
- Tpd DIN (max) > Tpd Clk (min)
     - setup time == Tpd DIN (max) - Tpd Clk (min)
- Tpd DIN (min) < Tpd Clk (max)
      - hold time  ==  Tpd Clk (max) - Tpd DIN (min)

for example for combinational logic delays are:
data path (max, min) = (5ns, 4ns)
clock path (max, min) = (4.5ns, 4.1ns)
then setup time = 5 - 4.1 = 0.9ns
hold time = 4.5 - 4 = 0.5ns

Now similar type of explanation we can give for a D flip-flop.  There is a combinational logic between C and Q, between D and Q of the flipflop. There are different delays in those combinational logic and based on there max and min value, a flipflop has setup and hold time. One circuitry of the positive edge triggered D flip is shown below.

 
 There are different ways for making the D flip-flop. Like by JK flip-flop, master slave flipflop, Using 2 D type latches etc. Since the internal circuitry is different for each type of flipflop, setup and hold time is different for every flip-flop.

Definition:
Setup Time:
- setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. This applied to synchronous circuits such as flipflop.
- or in short I can say that amount of time the Synchronous input (D) must be stable before the active edge of the clock.
- The time when the input data is available and stable before the clock pulse is applied is called setup time.

Hold Time:
- Hold time is the minimum amount of time the data signal  should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous circuits such as the flipflop.
- or in short I can say that amount of time the synchronous input (D) must be stable after active edge of the clock.
- the time after clock pulse where data input is held stable is called hold time.

setup and hold violation:
in simple language-
if setup time is Ts for a flip-flop and if data is not stable before the Ts time from active edge of the clock,  there is a setup violation at that flipflop. So if data is changing in the non-shaded area ( in the above figure) before active clock edge, then it's a setup violation.
And if hold time is Th for a flipflop and if data is not stable after Th time from active edge of the clock, there is a hold violation at that flipflop. So if data is changing in the non-shaded area ( in the above figure) after active clock edge, then it's a hold violation.