Clock Path may be passed through a "gated element" to achieve additional advantages. In this case, characteristics and definitions of the clock change accordingly. We call this type of clock path as "gated clock path".
As in the following fig you can see that,
LD pin is not a part of any clock but it is using for gating the original clock signal. Such type of paths are neither a part of clock path nor of data path because as per the Start Point and End Point definition of these paths, its different. So such type of paths are part of clock gating path.
Asynchronous Path:
A path from an input port to an asynchronous set or clear pin of sequential element.
See the following fig for understanding clearly,
As you know that the functionality of set/reset pin is independent from the clock edge. Its level triggered pins can start functioning at any time of data. So in other way we can say that this path is not in synchronous with the rest of the circuit and that's the reason we are saying such type of path Asynchronous Path.
Other Type of Paths:
There are few more type of paths which we usually use during timing analysis reports. Those are subset of above mention paths with some specific characteristics. Since we are discussing about the timing paths, so it will be good if we will discuss those here also.
Few Names are
critical path
false path
multi-cycle path
single cycle path
launch path
capture path
longest path (also know as Worst Path, Late Path, Max Path, Maximum Delay Path)
shortest path (also know as Best Path, Early Path, Min Path, Minimum Delay Path)
Critical Path:
In short, we can say that the path which creates longest delay is the critical path.
- Critical Paths are timing sensitive functional paths, because of the timing of these paths is critical, no additional gates are allowed to be added to the path, to prevent increasing the delay of the critical paths.
- Timing critical path are those path that do not meet your timing. What normally happens is that after synthesis the tool will give you a number of path which have a negative slag. The first thing you would do is to make sure those path are not false or multi-cycle path since it that case you can just ignore them.
Take a typical example ( in a very simpler way), the STA tool will add the delay contributed from all the logic connecting the Q output of one flop to the D input of the next (including the CLK->Q of the first flop), and then compare it against the defined clock period of the CLK pins ( assuming both flops are on the same clock, and taking into account the setup time of the second flop and the clock skew). This should be strictly less than the clock period defined for that clock. If the delay is less than the clock period , then the ' path meets the timing'. If it is greater, then the 'path fails timing'. The 'critical path' is the path out of all the possible paths that either exceeds its constraint by the largest amount, or , if all paths pass, then the one that comes closest to failing.
False Path:
- Physically exist in the design but those are logically/functionally incorrect path. Means no data is transferred from Start Point to End Point. There are maybe several reasons of such path present in the design.
- Some time we have to explicitly define/create few false path with in the design. E.g, for setting a relationship between between 2 Asynchronous Clocks.
- The goal in static timing analysis is to do timing analysis on all "true" timing paths, these paths are excluded from timing analysis.
- Since false path are not exercised during normal circuit operation, they typically don't meet timing specification , considering false path during timing closure can result into timing violations and the procedure to fix would introduce unnecessary complexities in the design.
- There may be few paths in your design which are not critical for timing or masking other paths which are important for timing optimization , or never occur with in normal situation. In such case, to increase the run time and improving the timing result, sometime we have to declare such path as a False Path, so that Timing analysis tool ignore these paths and so the proper analysis with respect to other paths. Or During optimization don't concentrate over such paths. One example of this, e.g A path between two multiplexed blocks that are never enabled at the same time. You can see the following the picture for this.
Here you can see that False path 1 and False Path 2 can not occur at the same time but during the optimization it can effect the timing of another path. So in such scenario, we have no define one of the path as false path.
Same thing I can explain in another way, (Note- Took snapshot from one of the forum). As we know that, not all paths that exist in a circuit are "real" timing paths. For example, let us assume that one of the primary inputs to the chip is a configuration input ; on the board it must be tied to either to VCC or to GND. Since this pin can never change, there are never any timing events on that signal. As a result, all STA paths that start at this particular start point are false. The STA tool (and the synthesis tool) cannot know that this pin is going to be tied off, so it needs to be told that these STA paths are false, which the designer can do by telling the tool using a "false_path" directive. When told that the paths are false. the STA tool will not analysis it ( and hence will not compare it to a constraint, so this path can not fail), nor will a synthesis tool do any optimization on that particular path to make it faster; synthesis tools try and improve paths until they "meet timing" - since the path is false, the synthesis tool has no work to do on this path. Thus, a path should be declared false if the designer KNOWS that the path in question is not a real timing path, even though it looks like one to the STA tool. One must be very careful with declaring a path false. If you declare a path false , and there is ANY situation where it is actually a real path, then you have created the potential for a circuit to fail, and for the most part, you will not catch the error until the chip is on a board, and (not) working. Typically , the false path exists
- from configuration inputs like the one described above
- from "test" inputs, inputs that are only used in the testing of the chip, and are tied off in normal mode ( however, there may still be some static timing constraints for the test mode of the chip).
- from asynchronous inputs to the chip ( and you must have some form of synchronizing circuit o this input) ( this is not an exhaustive list, but covers the majority of legitimate false paths).
So we can say that false paths should NOT be derived from running the STA tool ( or synthesis tool); they should known by the designer as part of the definition of the circuit, and constrained accordingly at the time of initial synthesis.
MultiCycle Path:
- A multi-cycle path is a timing path that is designed to take more than one clock cycle for the data to propagate from the startpoint to endpoint.
A multi-cycle path is a path that is allowed multiple clock cycles for propagation. Again, it is a path that starts at a timing startpoints and ends at timing ends point. However, for a multi-cycle path, the normal constraint on this path is overridden to allow for the propagation to take multiple clocks.
In the simplest example, the startpoint and endpoint are flops clocked by the same clock. The normal constraint is therefore applied by the definition of the clock; the sum of all delays from the CLK arrival at the first flop to the arrival at the D at the second clock should take no more than 1 clock period minus the setup time of the second flop and adjusted for clock skew.
By defining the path as a multi-cycle path you can tell the synthesis or STA tool that the path has N clock cycles to propagate; so the timing check becomes "the propagation must be less than
N x clock-period, minus the setup time and clock skew", N can be any number greater than 1.
Few example are
- When you are doing clock crossing from two closely related clocks; ie, from 30Mhz clock to 60 Mhz clock ,
-assuming the two clocks are from the same clock source (i.e. one is the divided clock of the other), and the two clocks are in phase.
-The normal constraint in this case is from the rising edge of the 30MHz clock to the nearest edge of the 60MHz clock, which is 60 ns later. However, if you have a signal in the 60MHz domain and that indicates the phase of the 30MHz clock, you can design a circuit that allows you for the full 33ns for the clock crossing, then the path from flop30 -> flop60 is a MCP (again with N = 2).
- The generation of the signal 30MHz_is_low is not trivial, since it must come from a flop which is clocked by the 60MHz clock, but show the phase of the 30MHz clock.
- Another place would be when you have different parts of the design that run at different, but related frequencies. Again, consider a circuit that has some stuff running at 60MHz and some running on a divided clock at 30MHz
- Instead of actually defining 2 clocks, you can use only the faster clock, and have a clock enable that prevents the clock in the slower domain from updating every other clocks.
- Then all the path from the "30MHz" flops to the "30MHz" flops can be MCP.
- This is often done since it is usually a good idea to keep the number of different clock domains to a minimum.
Single Cycle Path:
A single cycle path is a timing path that is designed to take only one clock cycle for the data to propagate from the startpoint to endpoint.
Lunch Path and Capture Path:
Both are inter-related so I am describing both in one place. When a flip-flop path to flip-flop path such as UFF1 to UFF3 is considered, one of the flip-flop launches the data and other captures the data. So here UFF1 is referred to "launch flip-flop" and UFF3 referred to "capture flip-flop".
These launch and capture terminology are always referred to a flip-flop to flip-flop path. (Means for this particular path (UFF1 > UFF3), UFF1 is launch flip-flop and UFF3 is capture flip-flop. Now if there is any other path starting from UFF3 and ends to some other flip-flops (let's assume UFF4), then for that path UFF3 become launch flip-flop and UFF4 be as capture flip-flop.
The name "launch path" referred to a part of clock path. Launch path is launch clock path which is responsible for launching the data at launch flip-flop.
And similarly capture path is also a part of clock path. Capture path is capture clock path which is responsible for capturing the data at capture flip-flop.
This is can be clearly understood by following fig,
Here UFF0 is referred to launch flip-flop and UFF1 as capture flip-flop for "data path " between UFF0 and UFF1 . So start point for this data path is UFF0/CK and end point is UFF1/D.
One thing we want to add here,
- Launch path and data path together constitute arrival time of data at the input of capture flip-flop.
- Capture clock period and its path delay together constitute required time of data at the input of capture register.
Note: It's very clear that capture and launch path are correspond to Data path. Means some clock path can be a launch path for one data path and be a capture path for another datapath . It will be clear by following fig,
Here you can see that for Data Path1 the clock path through BUF cell is a capture path but for Data Path2 its a launch path.
Longest and shortest Path:
Between any 2 points , there can be many paths.
Longest path is the one that takes longest time, this is also called worst path or late path or a max path.
The shortest path is the one that takes the shortest time; this is also called the best path or early path or a min path.
In the above fig, the longest path between the 2 flip-flop is through the cells UBUF1, UNOR2, and UAND3. The shortest path between the 2 flip-flops is through the cell UNAND3.
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