Static Timing Analysis: Timing Paths

Static Timing Analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations under worst-case conditions. It considers the worst possible delay through each logic element, but not the logical operation of the circuit.

In comparison to circuit simulation, static timing analysis is
.  faster -- It is faster because it does not need to simulate multiple test vectors.
.  more thorough -- It is more thorough because it checks the worst-case timing for all possible logic conditions, not just those sensitized by a particular set of test vectors.

Once Again Note Those Thing: Static Timing Analysis checks the design only for proper timing, not for correct logical functionality.

Static Timing Analysis seeks to answer the question, "Will the correct data be present at the data input of each synchronous device when the clock edge arrives, under all possible conditions?"

In static timing analysis, the word static alludes to the fact that this timing analysis is carried out in an input independent manner. It locates the worst-case delay of the circuit over all possible input combinations. There are huge of numbers of logic paths inside a chip of complex design. The advantage of STA is that it performs timing analysis on all possible paths ( whether they are real or potential false paths)
However, it is worth noting that STA is not suitable for all design styles. It has proven efficient only for fully synchronous designs. Since the majority of chip design is synchronous, it has become a mainstay of chip design over the last few decades.

The Way STA is performed on a given circuit:
To check a design for violations or say to perform STA there are there are 3 main steps:
. Design is broken down into sets of timing paths.
. Calculates the signal propagation delay along each path.
. And checks for violations of timing constraints inside the design and at the input/output interface.

The STA tool analyzes ALL paths from each and every startpoint to each and every endpoint and compares it against the constraint that (should) exist for that path. All path should be constrained, most paths are constrained , most paths are constrained by the definition of the period of the clock, and the timing characteristics of the primary inputs and outputs of the circuit.

Before we start this we should know a few key concepts in STA method:
timing path, arrive time, required time, slack and critical path.
Let's talk about these one by one in detail.

Timing Paths:
Timing Paths can be divided by as per the type of signals ( e.g. clock signal, data signal, etc)

Type of Paths for timing analysis :
- Data Path
- Clock Path
- Clock Gating Path
- Asynchronous Path

Each Timing Path has a "start point" and an "end point".  Definition of Start Point and End Point vary as per the type of the timing path-. The Start Point is a place in the design where data is launched by a clock edge. The data is propagated through combinational logic in the path and then captured at the endpoint by another clock edge.

Startpoint and Endpoint are different for each type of paths. It's very important to understand this clearly to understand and analysing the Timing Analysis Report and Fixing the timing violation.

- Data Path
    - Start Point
       Input Port of the Design ( because the input data can be launched from some external source).
       Clock Pin of the flip-flop/latch/memory ( sequential cell)
    - End Point
        Data Input Pin of the flip-flop/latch/sequential cell)
        Output Port of the design (because the output data can be captured by some external sink).

- Clock Path
     - Start Point
        Input Port of the design
     -  End Point
        Set/Reset/Clear Pin of the flip-flop /latch/sequential cell

Data Paths:

If we use all the combinational of 2 types of Starting Point and 2 types of End Point, we can say that there are that there are 4 types of timing paths on the basis of Start Point and End Point.
 - Input Pin/Port to Register (flip-flop).
 - Input Pin/port to Output Pin/Port
 - Register (flip-flop) to Register (flip-flop)
 - Register (flip-flop) to output pin/port.

Please see the following fig:

PATH1 - starts at an input port and ends at the data input of a sequential element.(input port to           register)
PATH2 - starts at the clock pin of a sequential element and ends at the data input of a sequential element. ( register to register )
PATH3 - starts at the clock pin of a sequential element and ends at an output port. (Register to output port)
PATH4 - starts at an input port and ends at an output port. ( Input port to output port).

Clock Path:
Please check the following fig:

In the above fig its very clear that for the clock path the starts from the input port/pin of the design which is specific for the Clock input and the end point is the clock pin of sequential element. In between the Start point and the end point there may be lots of buffers/inverters/clock divider.