Example Top_Level Implementation Flow with ILMs

1.  prepare the top level verilog file, if needed.

2.  set_analysis_views -setup {module_slowCorner} -hold {module_fastCorner}

3.  Load the config file, including the top-level netlist,  ILM directory name, ilm_blocks.lib

loadConfig fileName
specifyilm -cell block_A -dir ../block_A/block_A ILM
specifyilm -cell block_B -dir ../block_B ILM

4. load the floorplan

loadFPan top_floorplan

5. Place the design
placeDesign

6. Run pre_CTS timing optimization.
optDesign -preCTS

7. Build the clock tree
clockDesign

8. Run post-CTS timing optimization
Or
optDesign -postCTS -hold  ; #optional

9. Route the design
routeDesign

10. Run post-route optimization for setup
optDesign -postRoute

11. Run post-route optimization for setup and hold.
optDesign -postRoute -hold

12. Run post-route optimization for SI
optDesign -postRoute -si