STA

It is said as static because the timing information is obtain through calculation, not by simulation.

STA analysis the delay of all paths register to register, input to register, register to output and check if there is a violation.

If the delay of one path is too large, there will be setup violation.  The target register will sample the old value.

If the delay of one path is too small, there will be hold tie violation. The target register will sample the next value.

Both of two situation will cause error.