Clock Tree synthesis is performed to meet clock timing constraints, such as clock skew , latency (insertion delay), and the transition time.
General Issues caused by improper CTS:
1. Routing Congestion
2. Sudden Rise in Stdard cell Density
3. Timing closure Issues.
Best CTS will yield:
1. Reasonable density change
2. Well controlled CTS structure, in turn, yields best Insertion /skew / clock transitions.
3. Early timing closure
4. Less prone to Cross talks.
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