wire load models and back-annotated delay

To accurately calculate net delays, PT needs info. about the parasitic loads of the wire interconnections. Before placement and routing have been completed, PT estimates these loads by using wire load models provided  in the technology library. The set_wire_load_model cmd specifies which wire load model to use for the current analysis.

After placement and routing, you shold back-annotate the design with detailed net delay information using read_sdf cmd or detailed parasitic resistance and capacitance info. using the read_parasitics cmd. This information overrides the wire load models, allowing PT to perform a layout-accurate timing analysis.