clock skew and insertion delay (2)

Why clock tree needed in synchronous asic design ?
two resaons:
1. to maintain a reasonable rising time of the clock signal
2. to help reduce clock skew

what is clock skew?
Clock Skew is the difference of clock arriving time at the DFF's clock pin

How to improve clock skew?
use a clock tree

What is max insertion delay?
Max insertion delay is the longest delay from the clock source point to the DFF clock pin in a clock newwork.

How to improve max insertion delay?

max insertion delay depends on several facts,
1. the number of DFFs the clock is driving
2. the die area the DFFs scattered.
to reduce max insertion delay, you need to reduce the area, minimize the  number of DFFs that driven by a single clock, this may lead to changing your clocking strategy.