floorplan

Floorplanning is the process of defining the chip-size, placing the macrocell and placing I/O pads .
At this stage you can do an estimate for routing requirements etc.

Floorplanning is the process of creating core and IO areas with row defined in the core area. Each row will be divided into a minimum unit of area called SITE. Any placed cell will occupy one or more these sites. The floorplan can be created as soon as the netlist and the LEF is read into the backend tool. After floorplan you can get parameters like area of the die, utilization etc.

The output format of the floorplan depends on the tool used to do the floorplan , but .def is the design exchange format accepted by all the tools, and using all the tools we can dump out the .def file, it contains the physical location of the pins, macros which are used in the design.