what is clock latency?

The first important point is that there are two phases in the design of a clock signal.

At first the clock is in "ideal mode"( e.g:: during RTL design, during synthesis and during placement).  An "ideal" clock has no physical distribution tree, it is just shows up magically on time at all the clock pins.

The second phase comes when clock source pin to the (thousands) of flip-flop that need to get it.
CTS is done after placement and before routing. After CTS is finished, the clock is said to be in "propagated mode."

Now, what is clock latency?  Clock latency is an ideal mode term. It refers to the delay that is specified to exist between the source of the clock signal and the flip-flop clock pin.
That is delay specified by the user -- not a real measured thing. ( In fact, there is 'clock source latency' and 'clock network latency' -- the difference is not important for this discussion ). When the clock is actually created, then the same delay is now referred to as the "insertion delay."  Indertion Delay (ID) is a real, measurable delay path through a tree of buffers. Sometimes the clock latency is interpreted as desired target value for the insertion delay.