IR Drop

IR Drop as said above is voltage drop from the PAD circuitry to the standard cells.

>The implication is the reference voltage VDD is different at different places in the chip causing on chip variations. Also a negative impact on timing due to reduced VDD ==> ( VDD - I*R)

>To keep the IR Drop ( Voltage Drop ) within a particular range, we generally do power planning, by deliving

-- The number of core power pads
-- The core ring width
-- The core straps (Mesh) width & spacing & Number

##REF: Power Network design for an ASIC with Peripheral IO Power PADS ( Solvnet) for detailed calculations.

Note: This power planning is effectively nothing but Kirchoffs current law.