clock skew and insertion delay

why clock tree needed in synchronous asic design ?
what is clock skew ?
how to improve clock skew ?
what is max insertion delay ?
how to improve max insertion delay ?


Clock Tree is needed to ensure that the clock signal ( from the clock source to logical cell ) are synchronised at the same time with the same clock delay.


Clock skew is the variation of arrival time ( of the clock signal ) to the destination logic cell using the same clock source .  Clock skew is due to  (1) variation in the RC of the clock interconnect due to the geometrical layout of the length and width.  (2) process variation in permittivity and thickness ( due to the actual fabrication of the interconnect),  thus causes imperfection.

To improve clock skew,
1.  Use clock tree,  with branches as short as possible to reduce R and C, and using wider width for
     the higher branches closer to the clock source.

2.  Use a  DLL ( delay lock loop)

3.  Avoid using clock interconnect over many layers. Try to design the clock interconnect on the same metal layer or within 2 layers in order to reduce vertical resistance due to vias, which is highly resistance.

4. Maximum insertion delay = setup time + hold time + maximum propagation delay of the logic cell + maximum time of flight ( propagation delay of the interconnect )

To improve max insertion delay,
1. Reduce maximum time of flight
2. Reduce propagation delay of logic cell.
3. Reduce critical path in the logic cell
4. Alternatively , expand maximum insertion delay by re-timing.