Analyzing the Clock Tree Results

After synthesizing the clock trees, analyze the results to verify that they meet your requirements. Typically the analysis process consists of the follwoing tasks:

1. Analyzing the clock tree reports
2. Analyzing the clock tree timing
3. Verifying the placement of the clock instances, using the ICC GUI.

If the clock trees meet your requirements, you are ready to analyze the entire design for quality of results.

If the synthesis results do not meet your requirements, ICC can help you debug the results by outputting addtional information during clock tree synthesis. Set the cts_use_debug_mode variable to true before running clock tree synthesis to output the follwoing addtional information:
1)User-defined design rule constraints ( maximum transition time, maximum capacitance, and maximum fanout)
2)user-defined clock tree timing constraints
3)user-defined level restrictions (maximum level count )
4)Clustering targets set by ICC

In addtion, you can output detailed characterization data for the clock tree references by setting the cts_do_characterization variable to true.

Using this information, you can change the clock tree definitions to improve your results.