Timing Analysis

After you set the timing constraints such as clocks, input delays, and output delays, it is a good idea to use the check_timing command to check for timing setup problems and timing conditions such as incorrectly specified generated clocks and combinational feedback loops.  The command checks the timing attributes of the current design and issues warning messages about any unusual conditions found.

This is the full syntax of the check_timing command:

check_timing
    [-overlap_tolerance  minimum_distance]
    [-override_defaults  check_list ]
    [-include  check_list]
    [-exclude  check_list]
    [-multiple_clock]
    [-retain]

These are the types of timing checks that can be performed:

clock_timing
data_check_multiple_clock
data_check_no_clock
generated_clocks
generic
loops
multiple_clock
no_input_delay
retain
unconstrainted_endpoints
pulse_clock_cell_type
gated_clock
ideal_timing
clock_no_period

The types of timing checks are performed by default. You can include or exclude specific types of timing checks by using the -include and -exclude options or by setting the timing_check_defaults variable.

After placement, you can use the report_timing command to report the worse-case timing paths in the design. This is the command syntax:

report_timing
    [-to to_list]
    [-from from_list]
    [-through through_list]
    [-path short | full | full_clock | full_clock_expanded | only | end ]
    [-delay min | min_rise | min_fall | max | max_rise | max_fall ]
    [-nworst paths_per_endpoint]
    [-max_paths max_path_count]
    [-input_pins]
    [-nets]
    [-transition_time]
    [-crosstalk_delta]
    [-capacitance]
    [-attributes]
    [-physical]
    [-slack_greater_than greater_slack_limit]
    [-slack_lesser_than  lesser_slack_limit]
    [-lesser_path max_path_delay]
    [-greater_path min_path_delay]
    [-loops]
    [-true  [-true_threshold path_delay]]
    [-justify]
    [-enable_preset_clear_arcs]
    [-significant_digits digits]
    [-nosplit]
    [-sort_by group  | slack ]
    [-group  group_name]
    [-trace_latch_borrow]
    [-derate]
    [-scenario scenario_list ]
    [-temperatuew]
    [-voltage]

By default, the command reports the path having the worst maximum (setup) delay in each clock group. Net delay are based on estimated route lengths.

icc_shell> report_timing
..
Startpoint:   I_SDRAM_TOP/I_SDRAM_IF/DQ_out_1_reg_8_
                   (falling edge-triggered flip-flop clocked by SDRAM_CLK)
Endpoint:    sd_DQ_out[8]
                   (output port clocked by SD_DDR_CLK)
Path Group:  SD_DDR_CLK
Path Type:  max

....

The default report shows the startpoint, endpoint, path group ( clock domain), path type (minimum delay, maximum delay, max_rise, min_fall, and so on), the incremental and cumulative time delay values along the data and clock paths, the data required time at the path endpoint, and the timing slack for the path.

The report_timing command options let you specify the scope of paths reported (from/to/through specified points in the design), the path types reported, the numbers of worst-case paths reported,
and the types of information reported for intermediate points in the path (transition times, capacitance, net delays , and so on).

Analyzing Timing Paths

The timing nnalysis window provides a centralized area for performing timing path analysis. The window includes a timing analysis driver, a path inspector, and other analysis tools such as histograms, schematics, path profiles, and timing reports.

You can use tools in the timing analysis window to perform both high-level and detailed analyses of the timing paths in your design. You can
- Examine timing path details in the timing analysis driver
- View histograms that show the distribution of worst path slack, endpoint slack, net capacitance, or other path details in histogram views.
- Inspect the clock network and path data elements for a selected path in the path inspector.
- View path delay profiles for selected paths in path profile views.
- View selected paths, fanin and fanout cones, and other objects in path schematics.
- View and save timing reports for selected paths or the paths with the worst slack in the design.

The following sections describe the timing analysis tools:
Opening a Timing Analysis Window
When you open a timing analysis window, you can set the criteria for displaying timing path details in the timing analysis driver. By default, the details for the 20 worst paths in each path group are displayed.
To open a timing analysis window,
1. Choose Window > New Timing Analysis Window.
    The select Paths dialog box appears.
2. (Optional) To display path details in the window, select a method for choosing the paths, and select     other options as needed.
3. Click OK or Apply.


To get a detailed report on the delay calculation at a given point along a timing path, use the report_delay_calculation command. This is the command syntax:

report_delay_calculation
    [-min]  [-max]
    -from from_pin-to  to_pin
    [-nosplit]
    [-crosstalk]
    [-from_rise_transition value]
    [-from_fall_transition value]

Specify the "from" and "to" pins of the cell or net that you want to report. These two pins can be the input and output pins of  a cell to report the calculation of a cell delay, or can be the driver pin and a load pin of a net to report the calculation of a net delay. For Example, the following command reports in detail the delay calculation between two pins of  a cell:

icc_shell> report_delay_calculation \
                 -from I_SDRAM_TOP/I_SDRAM_IF/DQ_out_1_reg_8_/CPW \
                 -to I_SDRAM_TOP/I_SDRAM_IF/DQ_out_1_reg_8_/Q
...