CTS Prerequisites

Prerequisites for Clock Tree Synthesis

Before you run clock tree synthesis, ensure that your design and libraries meet the prerequisites described in the following sections.

Design Prerequisites

Before running clock tree synthesis, your design should meet the following requirements:

1) The design is placed and optimizaed.
Use the check_legality -verbose command to verify that the placement is legal.
Running clock tree synthesis on a design that does not have a legal placement might result in a long runtimes and reduced QoR.

The estimated QoR for the design should meet your requirements before you start clock tree synthesis. This includes acceptable results for

1) Congestion
If congestion issues are not resolved before clock tree synthesis, the addition of clock trees can increase congestion. If the design is congested, you can rerun place_opt with the -congestion and
-effort high options, but the runtime can be long.

2)Timing
3)Maximum Capacitance
4)Maximum Transition Time

To ensure that the clock tree can be routed, verify that the placement is such that  the clock sinks are not in narrow channels and that there are no large blockages between the clock root and its sinks. If these conditions occur, fix the placement before running clock tree synthesis.

5)The power and grounds nets are prerouted.

6)High-fanout nets, such as scan enables, are synthesized with buffers.

Library Prerequisites
Before you run clock tree synthesis, your libraries must meet the following requirements:

1)Any cell in the logic library that you want to use as a clock tree reference ( a buffer or inverter cell that can be used to build a clock tree) or for sizing of gates on the clock network must be usable by clock tree synthesis and optimization.

By default, clock tree synthesis and optimization cannot use buffers and inverters that have the dont_use attribute to build the clock tree. To use these cells during clock tree synthesis and optimization, you can either remove the dont_use attribute by using the rmove_attribute command or you can override the dont_use attribute by specifying the cell as a clock tree reference by using the set_clock_tree_reference command.

2) The physical library should include
-- All clock tree reference (the buffer and inverter cells that can be used to build the clock trees)
-- routing information, which inludes layer information and nondefault routing rules

3) TLUPlus modeels must exist.
Extraction requires these models to estimate the net resistance and capacitance.