Cascaded Clocks

If a netsed clock tree has its own source, ICC considers the source pin of the driven clock (clk2 in this example) to be an implicit exclude pin of the driving clock (clk1 in this example). Sinks of the driven clock are not considered sinks of the driven clock.

Cascaded Clock With Two Source Clocks

To Verify that the clock sources are correctly defined, use the check_clock_tree command.

Cascaded Generated Clocks

If a nested clock tree has a generated source, ICC traces back to the master clock source from which the generated clock is derived and considers the sinks of the generated clock to be the sinks of the driving clock tree.

Cascaded Clock With Generated Clock

Incorrectly defining the master clock source,  as in the follwoing cases, results in poor skew and timing QoR.

1) IF ICC cannot trace back to the master clcok source, the tool  cannot balance the sinks of the generated clock with the sinks of its source.

2) IF the master clock source is not a clock source defined by create_clock or create_generated_clock , ICC cannot synthesize a clock tree for the generated clock or its source.

Use the check_clock_tree command to verify that your master clock sources are correctly defined.

If a nested clock tree has a generated source that is defined at the intersection of overlapping clocks, ICC traces back to the master clock source from which the generated clock is derived and considers the source pin of the generated clock on a per clock basis during synthesis. By default, ICC clock tree synthesis supports querying phase delay and clock tree exceptions for each clock domain to achieve the best QoR for cascaded generated clocks with overlapping clocks.

For Example, Assume the flip-flop inside the clk1 and clk2 overlapping domains has a generated clock, genclk2, which is defined at its Q output and which uses clk2 as the master clock. If you perform clock tree synthesis on clk2, the clock tree after that flip-flop is synthesized and balanced as a generated clock of clk2.

cascated generated clock with overlapping clock domains