Inserting Spare Cells

You insert them before or after placement and used them when placement is fixed.
With spare cells, you can perform simple logic changes by updating only one or a few metal and via masks, thereby saving the considerable expense of generating a whole new set of silicon-layer masks.

Spare cells are most useful when they are physically near the location of the logic that needs to be changed. Therefore, spare cells need to be dispersed across the chip rather than gathered in one or several tight locations.

To add and place spare cells in a design, do one of the following steps:

1) Manually instantiate the spare cells into the verilog netlist
Do this before reading the netlist into the ICC. There is no RTL description for spare cells; You must instantiate all spare cells.

2)Use the insert_spare_cells command
Run this cmd to insert a specified number of specified library cells into a legally placed design.
The new cells can be evenly distributed and legalized. These addtional cells do not affect existing placement. The command does not remove any existing spare cells.

Inserting Spare Cells Using a Verilog Netlist
There is no limit to the number of spare cells you can add to the design. This allows you the flexbility to break up the spare cells so that they can be easily scattered or be located near one specific logic that might be more likely ro require an ECO.

Usually the spare cells are instantiated and grouped in seperate hieratchical blocks.
However, if you want to place a group of spare cells near one specific logic, you can break the hierarchical blocks into multiple blocks. This enables you to place a group of spare cells physically near its related logic.

The spare cells inputs can be connected to high or low logic levels. To prevent the gate from oscillating ( create noise and consuming power), tie the inputs to ground or power, as appropriate.
The spare gates are usually independent, but you can connect thenm together to form other functions. In any case, you must instantiate each spare cell in the netlist.
1) Automatically place the spare cells during placement.
2)Manually place the spare cells before placement.
3)Manually place the spare cells after placement.

Automatically Distributing the Spare Cells During Placement
Note:
Automatic spare cell placement work only for spare cells that have  all inputs tied low or high and have output ports that float. Addtionally, due to the current tool limitations, you must set the attribute is_spare_cell on the spare cells to enable the tool to place spare cells automatically. Any spare cells that are connected to signal nets, such as sequential cells connected to a clock, cannot be distributed automatically. You need to insert these spare cells manually.

After you add your spare cells into the Verilog netlist and import the netlist into ICC, the tool will distribute the spare cells automatically during placement. This placement is hierarchically aware, so you can insert spare cells in a logic submodule instead of across the entire design.