High-Fanout Net Synthesis

You can use the compile_clock_tree command to perform high_fanout net synthesis by using the -high_fanout_net nets_or_driving_pins option ( or by choosing Clock > Compile Clock Tree in the GUI and specifying the high-fanout nets in the "High fanout nets" field)

Note:
In a single compile_clock_tree run, you can perform either high-fanout net synthesis ( by specifying the -high_fanout_net option) or clock tree synthesis ( by specifying no clock names or by specifying the clock trees with the -clock_trees option); you cannot perform both tasks in a single run.

When you use compile_clock_tree -high_fanout_net to perform high_fanout net synthesis, the result is a balanced buffer tree ( called a high-fanout tree), which is similar to a clock tree. When you use the create_buffer_tree cmd to perform high-fanout net synthesis, the resulting buffer tree might not be balanced.

The compile_clock_tree cmd  performs high-fanout net synthesis by balancing the arrival times from the drivers of the nets specified in -high_fanout_net to the fanouts of those nets. High-fanout net synthesis does not traverse through preexisting gates on the high fanout net, nor does it support the use of clock tree synthesis.

Important:
If a clock tree exception exists on any fanout pin of a high-fanout net, high-fanout net synthesis generates an error message and fails. You must remove the clock tree exceptions and rerun high-fanout net synthesis.

By default, high-fanout clock tree synthesis can use any of the buffers or inverters in the library. To restrict the set of buffers or inverters used by high-fanout clock tree synthesis, use the
set_clock_tree_reference command.

High-fanout clock tree synthesis determines the clock tree design rules in the same way as standard CTS. To define the clock tree design rules, use the set_clock_tree_options cmd.

By default, high-fanout clock tree synthesis uses the rising edge to determine the skew and arrival times. To use the falling edge instead, use the -sync_phase fall option when you run compile_clock_tree. To use both edges, use the -sync_phase both option when you run compile_clock_tree.


When you perform high-fanout clock tree synthesis, neither the endpoints nor the inserted buffers are fixed after high-fanout net synthesis. This is to allow psynout to optimiza the timing of the high-fanout trees.

To report the skew and path delay of the synthesized high-fanout net, use the report_clock_tree
-high_fanout_net pins_or_nets cmd. You can use the following report_clock_tree options together with the -high_fanout_net option:
-summary, -structure, -level_info, -drc_violators, -operating_condition, and -nosplit. All other report_clock_tree options are not supported with -high_fanout_net.

High-fanout clock tree synthesis has the following limitations:
1) High-fanout clock tree synthesis does not support multicorner or multimode designs.
2)High-fanout clock tree synthesis does not insert level shifters or insolation buffers in multivoltage designs. You must insert the level shifters and isolation buffers before running high-fanout clock tree synthesis.
3)you cannot use optimize_clock_tree to optimize the high-hanout trees. Use the psynopt cmd instead.