CTS is the process of implementing the clock tress based on your requirements. CTS is performed during the clock_opt process and can also be run as a standalone process.
ICC CTS is bloakage_aware by default. The blockage_aware capability avoids routing and placement blockages to reduce DRC violations in designs with complex floorplans. Furthermore, it implements CTS with minimum clock insertion delays, small clock skew, low buffer count, and small clock cell area to produce the best QoR.
During CTS, ICC
1) Upsizes and moves the existing clock gates, which can improve the QoR and reduce the number of clock tree levels.
Note:
To prevent upsizing of specific cells during this process, use the
set_clock_tree_exceptions -dont_size_cell command.
2) Inserts buffers and inverters to build clock trees that meet the clock tree design rule constraints, while balancing the loads and minimizing the clock skew.
3)Fixes DRC violations beyond clock exceptions if the
cts_fix_beyond_clock_exceptions variable is set to true (the default).
4)Builds a blockage map infrastructure per voltage area to identify whether a location is blocked for routing or placement, so the legalizer can move buffers to the nearest unblocked locations toward clock sources.
5)Locates the shortest blockage-avoiding route path from a start point to an end point with minimum
delay to prevent DRC violations.
If your design has logical hierarchy, ICC uses the lowest common parent of a buffer's fanout pins to determine where to insert the buffers.
1. If the lowest common parent is not the top level of the design, the buffer is inserted in the lowest common parent.
2. If the lowest common parent is the top level of the design, the buffer is inserted in the block that contains the driving pin of the buffer.
ICC adds new ports to the subdesigns where needed. The ports are added such that a minimum number of new ports are added.
To perform standalone CTS, use the compile_clock_tree command ( or Choose Clock > Compile Clock Tree in the GUI and specify the clock trees in the "Clock tree names" field).
Note:
If you compile one clock at a time, be aware that the order in which you compile the clocks can affected the clock tree QoR. For best results, compile the most criticle clock first.
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