Insertion of Tie Cell

What stage do we insert the tie cells into the design?

It's the right way to insert the tie cells after the placement optimization is finished during PnR.
The reason is because the PnR tool isn't able to place the tie cells at the right location close to relative logics and optimize the tie cells.

If pre-layout netlist (logic synthesis) has the tie cells, that must be cause a serious routing congestion.

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Tie Cell Insertion
A tie cell is a special-purpose standard cell whose output is constant high ot constant low and is used to hold the input of another cell at the given constant value. To prepare the place_opt or psynopt commands for automatic insertion and optimization of tie-offs required in the design, execute commands similar to the following:

set_auto_disable_drc_nets -constant false
set_app_var  physopt_new_fix_constants true
set_attribute  [....] max_fanout  12
set_attribute  [....] max_capacitance  0.2  -type  float

Optimization means using a single tie cell to hold as many inputs as possible at a given logic level, while meeting specified maximum fanout and maximum capacitance constraints.  The set_auto_disable_drc_nets command enables DRC on constant nets. Setting the physopt_new_fix_constants variable to true causes ICC to observe the maximum capacitance constraint during tie-off optimization. The maximum capacitance constraint is determined by the max_capacitance attribute, which can be set with the set_max_capacitance  or  set_attribute command.  The set_attribute command can be used to specify explicitly both the maximum fanout and maximum capacitance constraints for objects in the design.

You can also insert tie cells manually with the connect_tie_cells cmd. The cmd insert tie cells and connects them to specified cell ports, while meeting the maximum fanout and maximum wire length constraints specified in the cmd.