Verifying the Clock Trees

Before you synthesize the clock trees, use the check_clock_tree command to verify that the clock trees are properly defined.

icc_shell> checcl_clock_tree -clocks my_clk

If you do not specify the -clocks option, ICC checks all clocks in the current design.

The check_clock_tree command checks for the follwoing issues:
- Hierarchical pin defined as a clock source
- Generated clock without a valid master clock sourece
  A generated clock does not have a valid master clock source in the following situations:
    1) The master clock specified in create_generated_clock does not exist.
    2) The master clock specified in create_generated_clock does not drive the source pin of the generated clock.
    3) The source pin of the generated clock is driven by multiple clocks, and some of the master clocks are not specified with create_generated_clock.

For example,

the reg01/Q pin is driven by both clka and clkb. If only clkb is apecified as a master clock in a create_generated_clock command, gen_clkb does not have a valid clock source.

4) Clock (master or generated ) with no sink  

5) Looping clcok

6) Cascated clock with  an unsynthesized clock tree in its fanout

7)Multiple-clocks-per-register propagation not enabled, but the design constains overlapping clocks.

8)Ignored clock tree exceptions

9)Stop pin or float pin defined on an output pin.

10)Buffers with multiple timing arcs used in clock tree references

11)Situations causing empty buffer list