Analyzing the Clock Trees

Before running clock tree synthesis, analyze each clock tree in your design to determine its characteristics and its relationship to other clock trees in the design.

For each clock tree, determine

1) What the clock root is
2) What the desired clock sinks and clock tree exceptions are
     ICC supports the following types of clock tree exceptions:  exclude pins, stop pins, float pins,              don't touch subtrees, don't buffer nets, and don't size cells.
3) Whether the clock tree contains preexisting cells, such as clock-gating cells
If your design contains existing clock trees, you might want to either identify them or remove them before running clock tree synthesis.
4) Whether the clock tree converges, either with itself ( a convergent clock path) or with another clock tree ( an overlapping clock path)
5) Whether the clock tree has timing relationships with other clock trees in the design, such as interclock skew requirements.
6) What the logical design rule constraints ( maximum fanout, maximum transition time, and maximum capacitance) are
7) What the routing constraints ( routing rules and metal layers ) are

Use this information when you define the clock trees and to validate that ICC has the correct clock tree definitions.