Hierarchical Designs Using Interface Logic Models

You can use interface logic models (ILMs) to increase the capacity and reduce the runtime for top-level clock tree synthesis. Brfore creating ILMs for use with top-level clock tree synthesis, you must perform clock tree synthesis on the blocks.

During clock tree synthesis and optimization, ICC
1) Identifies any ILMs inside a clock tree
When a clock defined at the top level goes through an ILM, ICC insert guide buffers before the ILM clock input pin and after the ILM clock output pins. The nets between the input guide buffer and output guide buffers are marked as don't buffer nets.

2)Honors clocks or generated clocks defined on an ILM port or a pin internal to the ILM
When a clock is defined on an ILM input port or in an ILM, ICC inserts guide buffers after the ILM clock output pins. Clock nets within the ILM ( up to the guide buffers) are marked as don't buffer nets.

3) Times the clock subtrees inside the ILM to calculate the phase and transition delays for the ILM
ICC uses the timing information for the clock trees within the ILM to perform skew balancing and insertion delay minimization up to the ILM clock input pins and beyond the ILM clock output pins.

If there are mulpiple subtrees after an ILM, ICC synthesizes each subtree independently and does not balance the insertion delay between them, which can result in large skew between them. To reduce this skew, run the optimiza_clock_tree command after performing clock tree synthesis.

4) Honors explicit stop pins, exclude pins, and sink pins on an ILM port or inside an ILM.