Analyzing Clock Tree

Before running clock tree synthesis, analyze each clock tree in your design to determine its characteristics and its relationship to other clock trees in your design.

For each clock tree, determine

1) what clock root is

2) what the desired clock sinks and clock tree exceptions are
ICC supports the following types of clock tree exceptions: exclude pins, stop pins, floating pins, don't touch subtrees, don't buffer nets, and don't size cells.

3)Whether the clock tree contains preexisting cells, such as clock-gating cells
If your design contains existing clock trees, you might want to either identify them or remove them before running clock tree synthesis.

4)Whether the clock tree converges, either with itself ( a convergent clock path) or with another clock tree ( an overlapping clock path)

5)Whether the clock tree has timing relationships with other clock trees in the design, such as interclock skew requirements

6)What the logical design rule constraints (maximum fanout, maximum transition time, and maximum capacitance) are

7)What the routing constraints ( routing rules and metal layers) are

Use this information when you define the clock trees and to validate that ICC has the correct clock tree definitions.

Note:
You can generate clock tree reports to analyze the clock tree structure, even before you perform clock tree synthesis and optimization.

Defining the clock trees

ICC uses the clock sources defined by the create_clock command as the clock roots and derives the default set of clock sinks by tracing through all cells in the transitive fanout of the clock roots. You can designate either an input port or internal hierarchical pin as a clock source.  To disallow clock sources defined on a hierarchical pin, set the cts_enable_clock_at_hierarchical_pin variable to false before using the create_clock command. This variable is true by default.

Note:
ICC will not synthesize a clock tree if its source is set to a constant value by using set_case_analysis.

In addtion to simple clock trees, ICC also supports cascaded clock trees ( a clock tree that contains another clock tree in its fanout).  The nested clock tree can either have its own source ( identified by the create_clock command) or be a generated clock (identified by the create_genrated_clock command).